This thesis demonstrate how pipelining in a RISC processor is achieved by implementing a subset of MIPS R2000 instructions on FPGA. Pipelining, which is one of the primary concepts to speed up a microprocessor is emphasized throughout this thesis. Pipelining is fundamentally invisible for high level programming language user and this work reveals the internals of microprocessor pipelining and the potential problems encountered while implementing pipelining. The comparative and quantitative flow of this thesis allows to understand why pipelining is preferred instead of other possible implementation schemes. The methodology for programmable logic development and the capabilities of programmable logic devices are also given as background information. This thesis can be the starting point and reference for programmers who are willing to get familiar with microprocessors and pipelining.

In this thesis, we address the problem of digital intellectual property (IP) protection for the field programmable gate array (FPGA) designs. Substantial time and effort is required to the design complex circuits; thus, it makes sense to re-use these designs. An IP developer can sell his design to the companies and collect royalty. However, he needs to protect his work from security breach and piracy. The legal means of IP protection such as patents and license agreements are a deterrent to illegal IP circulation, but they are insufficient to detect an IP protection breach. Watermarking provides a means to identify the owner of a design. Firstly, we propose a watermarking technique that modifies the routing of an FPGA design to make it a function of the signature text. This watermarking technique is a type of constraint-based watermarking technique where we add a signature-based term to the routing cost function. Secondly, we need a method to verify the existence of the watermark in the design. To address this we propose a digital signature generation technique. This technique uses the switch state (ON/OFF) of certain switches on the routing to uniquely identify a design. Our results show less than 10% speed overhead for a minimum channel width routing. Increasing the channel width by unit length, we could watermark the design with a zero speed overhead. The increase in the wire length is negative for majority of the circuits. Our watermarking technique can be integrated into the current routing algorithm since it does not require an additional step for embedding the watermark. The overall design effort for routing a watermarked design is equivalent to that of routing a non-watermarked design.

The emergence of a multitude of bandwidth hungry multimedia applications has ex- acerbated the need for multi-gigabit wireless solutions and made it out of the reach of conventional WLAN technology (802.11a, b and g). This thesis presents a system on chip which demonstrates the potential of 60GHz transceivers. This system is based on an FPGA board on which a GNU/Linux kernel has been run. This document will give some insight on the design process as well as on the finished product. Both the hardware and the software parts of the design are presented. This document is organized as follow. Chapter I presents an overview of the problem to be solved and some insight on the motivation to work at 60GHz. Chapter II gives a high level view of the multimedia processor that has been designed and implemented. Chapters III and IV respectively give more detail on the hardware parts and on the software components of the pro ject. Finally, Chapter V draws the conclusion of this work and presents the future of the work that has been started to enhance this multimedia processor.

Modern physical experiments often demand advanced instrumentation based on advances in  technology. This work describes four instrumentation physics projects that are based on modern, high-capacity Field-Programmable Gate Arrays, making use of their versatility, programmability, high bandwidth communication interfaces and signal processing capabilities. In the first project, a jet-finding algorithm for the ATLAS detector at the LHC experiment at CERN was developed and implemented, and different verification methods were created to validate the functionality and reliability. The experiment uses a three level trigger system, where the first level uses custom FPGA-based hardware for analysis of collision events in real-time. The second project was an advanced timing and triggering distribution system for the new European X-Ray Free Electron Laser (XFEL) facility at DESY in Hamburg. XFEL will enable scientists to study nano structures on the atomic scale. Its laser pulses will have the strongest peak power in the world with extremely short duration and a high repetition rate, which will even allow filming of chemical reactions. The timing system uses modern FPGAs to distribute high-speed signals over optical fibers and to deliver clocks and triggers with high accuracy. The third project was a new data acquisition board based on high-speed ADCs combined with high-performance FPGAs, to process data from segmented Ge-detectors in real-time. The aim was to improve system performance by greatly oversampling and filtering the analog signals to achieve greater effective resolution. Finally, an innovative solution was developed to replace an aging system used at CERN and Stockholm University to test vital electronics in the Tile Calorimeters of the ATLAS detector system. The new system is entirely based on a commercial FPGA development board, where all necessary custom communication protocols were implemented in firmware to emulate obsolete hardware. / Inom området instrumenteringsfysik bedrivs forskning och utveckling av avancerade instrument, som används inom moderna fysikexperiment. Denna avhandling beskriver fyra projekt där programmerbara kretsar (FPGA) har nyckelfunktioner för att lösa krävande instrumenteringsuppgifter. Den första projektet beskriver utveckling och implementering av en algoritm för detektering av partikelskurar efter partikelkollisioner i LHC-experimentets ATLAS-detektor. Experimentet genererar 40 miljoner händelser per sekund, som måste analyseras i real-tid med hjälp av snabba parallella algoritmer. Resultatet avgör vilka händelser som är tillräckligt intressanta för fortsatt noggrannare analys. Den andra projektet beskriver utvecklingen av ett system som distribuerar klock- och trigger-signaler över ett 3 kilometers experimentområde med extrem precision, i den nya röntgenlaseracceleratorn XFEL vid DESY i Hamburg. Vid XFEL kommer man utforska nanostrukturer och till och med filma molekylers kemiska reaktioner. I den tredje projektet beskrivs utvecklingen av ett höghastighets datainsamlingssystem, för segmenterade Ge-detektorer. Genom att översampla signalen med hög hastighet kan man uppnå en bättre noggrannhet i mätningen än vad AD-omvandlarens egna upplösning medger. Detta leder i sin tur  till förbättrade systemprestanda. Slutligen beskrivs en innovativ lösning till ett test system för den elektronik, som Stockholms universitet har levererat till ATLAS detektorn. Det nya systemet ersätter det föregående testsystemet, som är baserad på föråldrade inte längre tillgängliga komponenter. Det nya systemet är dessutom också billigare eftersom det är baserat på ett standard FPGA utvecklingskort. / ATLAS experiment of the Large Hadron Collider experiment / European X-ray Free Electron Laser

Masters Research - Master of Engineering / This thesis demonstrates the process of building a system to test multiple-input multiple-output (MIMO) communications over-the-air. It covers the entire process, from concept to design and construction, culminating in transmitting space-time coded data packets and producing bit error rate (BER) performance curves. A flexible modular architecture is designed, able to test current MIMO systems and to be upgraded as the field develops. Printed circuit boards for a field-programmable gate array (FPGA) based mainboard, 2.4 GHz transceivers and antennas are then designed, embodying the aforementioned architecture. The mainboard uses a Xilinx XC2S600E FPGA, with ∼600,000 logic gates. Hardware is assembled and tested, forming a foundation for further layers of firmware and software. An abstraction layer, with associated test benches, is written in a hardware description language (VHDL), allowing the core logic of the FPGA to be written and simulated in a device-independent manner. Further VHDL is written and the testbed configured to transmit and receive bursts of data. A device driver is implemented, and abstract data types are layered on top of the driver, enabling high-level control of the testbed. Single antenna and MIMO data links are implemented using 1x1 binary phase-shift keying (BPSK) and 2x2 Alamouti encoded BPSK modulation respectively. Finally, data packets are transmitted and measured BER performance curves constructed. Channel estimation is proved to work on a 2x2 MIMO channel over-the-air, the introduced loss of Eb/N0 shown to be approximately 0.5 dB compared to perfect channel information. The analogue limitations of the hardware are investigated and bit error rate performance measured as a function of operating point. Finally single antenna communications and a 2x2 Alamouti MIMO scheme are compared over-the-air, the Alamouti scheme delivering a 3 dB improvement in Eb/N0 performance. Satisfyingly the MIMO scheme also exceeds the best case theoretical performance bound of the single antenna case by a margin of 2 dB in Eb/N0.

This dissertation reports on studies of the application of lexicographic graph searches to solve problems in FPGA detailed routing. Our contributions include the derivation of iteration limits for scalar implementations of negotiation congestion for standard floating point types and the identification of pathological cases for path choice. In the study of the routability-driven detailed FPGA routing problem, we show universal detailed routability is NP-complete based on a related proof by Lee and Wong. We describe the design of a lexicographic composition operator of totally-ordered monoids as path cost metrics and show its optimality under an adapted A* search. Our new router, CornNC, based on lexicographic composition of congestion and wirelength, established a new minimum track count for the FPGA Place and Route Challenge. For the problem of long-path timing-driven FPGA detailed routing, we show that long-path budgeted detailed routability is NP-complete by reduction to universal detailed routability. We generalise the lexicographic composition to any finite length and verify its optimality under A* search. The application of the timing budget solution of Ghiasi et al. is used to solve the long-path timing budget problem for FPGA connections. Our delay-clamped spiral lexicographic composition design, SpiralRoute, ensures connection based budgets are always met, thus achieves timing closure when it successfully routes. For 113 test routing instances derived from standard benchmarks, SpiralRoute found 13 routable instances with timing closure that were unroutable by a scalar negotiated congestion router and achieved timing closure in another 27 cases when the scalar router did not, at the expense of increased runtime. We also study techniques to improve SpiralRoute runtimes, including a data structure of a trie augmented by data stacks for minimum element retrieval, and the technique of step tomonoid elimination in reducing the retrieval depth in a trie of stacks structure.

Masters Research - Master of Engineering / This thesis demonstrates the process of building a system to test multiple-input multiple-output (MIMO) communications over-the-air. It covers the entire process, from concept to design and construction, culminating in transmitting space-time coded data packets and producing bit error rate (BER) performance curves. A flexible modular architecture is designed, able to test current MIMO systems and to be upgraded as the field develops. Printed circuit boards for a field-programmable gate array (FPGA) based mainboard, 2.4 GHz transceivers and antennas are then designed, embodying the aforementioned architecture. The mainboard uses a Xilinx XC2S600E FPGA, with ∼600,000 logic gates. Hardware is assembled and tested, forming a foundation for further layers of firmware and software. An abstraction layer, with associated test benches, is written in a hardware description language (VHDL), allowing the core logic of the FPGA to be written and simulated in a device-independent manner. Further VHDL is written and the testbed configured to transmit and receive bursts of data. A device driver is implemented, and abstract data types are layered on top of the driver, enabling high-level control of the testbed. Single antenna and MIMO data links are implemented using 1x1 binary phase-shift keying (BPSK) and 2x2 Alamouti encoded BPSK modulation respectively. Finally, data packets are transmitted and measured BER performance curves constructed. Channel estimation is proved to work on a 2x2 MIMO channel over-the-air, the introduced loss of Eb/N0 shown to be approximately 0.5 dB compared to perfect channel information. The analogue limitations of the hardware are investigated and bit error rate performance measured as a function of operating point. Finally single antenna communications and a 2x2 Alamouti MIMO scheme are compared over-the-air, the Alamouti scheme delivering a 3 dB improvement in Eb/N0 performance. Satisfyingly the MIMO scheme also exceeds the best case theoretical performance bound of the single antenna case by a margin of 2 dB in Eb/N0.

Ecological modelling problems have characteristics both featured in other modelling fields and specific ones, hence, methods developed and tested in other research areas may not be suitable for modelling ecological problems or may perform poorly when used on ecological data. This thesis identifies issues associated with the techniques typically used for solving ecological problems and develops new generic methods for decision support, especially suitable for ecological data modelling, which are characterised by: (1) adaptive learning, (2) knowledge discovery and (3) accurate prediction. These new methods have been successfully applied to challenging real world ecological problems. Despite the fact that the number of possible applications of computational intelligence methods in ecology is vast, this thesis primarily concentrates on two problems: (1) species establishment prediction and (2) environmental monitoring. Our review of recent papers suggests that multi-layer perceptron networks trained using the backpropagation algorithm are most widely used of all artificial neural networks for forecasting pest insect invasions. While the multi-layer perceptron networks are appropriate for modelling complex nonlinear relationships, they have rather limited exploratory capabilities and are difficult to adapt to dynamically changing data. In this thesis an approach that addresses these limitations is proposed. We found that environmental monitoring applications could benefit from having an intelligent taste recognition system possibly embedded in an autonomous robot. Hence, this thesis reviews the current knowledge on taste recognition and proposes a biologically inspired artificial model of taste recognition based on biologically plausible spiking neurons. The model is dynamic and is capable of learning new tastants as they become available. Furthermore, the model builds a knowledge base that can be extracted during or after the learning process in form of IF-THEN fuzzy rules. It also comprises a layer that simulates the influence of taste receptor cells on the activity of their adjacent cells. These features increase the biological relevance of the model compared to other current taste recognition models. The proposed model was implemented in software on a single personal computer and in hardware on an Altera FPGA chip. Both implementations were applied to two real-world taste datasets.In addition, for the first time the applicability of transductive reasoning for forecasting the establishment potential of pest insects into new locations was investigated. For this purpose four types of predictive models, built using inductive and transductive reasoning, were used for predicting the distributions of three pest insects. The models were evaluated in terms of their predictive accuracy and their ability to discover patterns in the modelling data. The results obtained indicate that evolving connectionist systems can be successfully used for building predictive distribution models and environmental monitoring systems. The features available in the proposed dynamic systems, such as on-line learning and knowledge discovery, are needed to improve our knowledge of the species distributions. This work laid down the foundation for a number of interesting future projects in the field of ecological modelling, robotics, pervasive computing and pattern recognition that can be undertaken separately or in sequence.

Evolvable Hardware is a technique derived from evolutionary computation applied to a hardware design. The term evolutionary computation involves similar steps as involved in the human evolution. It has been given names in accordance with the electronic technology like, Genetic Algorithm (GA), Evolutionary Strategy (ES) and Genetic Programming (GP). In evolutionary computing, a configured bit is considered as a human chromosome for a genetic algorithm, which has to be downloaded into hardware. Early evolvable hardware experiments were conducted in simulation and the only elite chromosome was downloaded to the hardware, which was labelled as Extrinsic Hardware. With the invent of Field Programmable Gate Arrays (FPGAs) and Reconfigurable Processing Units (RPUs), it is now possible for the implementation solutions to be fast enough to evaluate a real hardware circuit within an evolutionary computation framework; this is called an Intrinsic Evolvable Hardware. This research has been taken in continuation with project 'Evolvable Hardware' done at Manukau Institute of Technology (MIT). The project was able to manually evolve two simple electronic circuits of NAND and NOR gates in simulation. In relation to the project done at MIT this research focuses on the following: To automate the simulation by using In Circuit Debugging Emulators (IDEs), and to develop a strategy of configuring hardware like an FPGA without the use of their company supplied in circuit debugging emulators, so that the evolution of an intrinsic evolvable hardware could be controlled, and is hardware independent. As mentioned, the research conducted here was able to develop an evolvable hardware friendly Generic Structure which could be used for the development of evolvable hardware. The structure developed was hardware independent and was able to run on various FPGA hardware’s for the purpose of intrinsic evolution. The structure developed used few configuration bits as compared to current evolvable hardware designs.

The ubiquity of Internet connectivity means there is a greater need for computer network safety and security. Cost-effective secure computing networks and broadband applications not only need a sophisticated cryptosystem to accelerate data encryption, but also need substantial computational power to handle large data streams. Reconfigurable System-on-Chip (rSoC) technology is well suited to accelerate network cryptographic applications by implementing the entire computing application on a single reconfigurable chip. Hardware-software co-design and hardware-software communication are some key questions involved in using this rSoC technology. This thesis investigates how best to accelerate a cryptographic application using rSoC technology. Some background on FPGAs, reconfigurable computing, inter-process communication methods, hardware/software co-design, cryptography in general, and 3DES in particular are firstly introduced. Some existing reconfigurable computing systems and 3DES implementations on FPGA are then reviewed and analyzed. A new general hardware-software architecture, which consists of a CPU, memories, customized peripherals and buses on a single FPGA chip, is designed to accelerate the security application. The 3DES application is divided into four functional modules: input, subkey generation, data processing, and output modules. Shared memory with semaphores is chosen for the inter-module communication. A complete inter-module communication solution is presented for hardware and software module communications. A generic component, HWCOM, is designed for those communications which involve hardware modules. Experimental results show that using two buffers as shared memories between communication modules and increasing shared memory size are good methods for transferring data between hardware/software modules more efficiently. When investigating the best hardware/software partition scheme, all 3DES modules are first executed in software on the FPGA. The experimental results of 83Kbps encryption throughput indicate that the software-only solution is not satisfactory. Through profiling, the bottleneck is shown to be the data processing module and the subkey generation module, which are then implemented in hardware. Experimental results show an improved 179Mbps throughput. This presents over 2000 times acceleration compared to software and shows that the hardware-software co-implementation can efficiently accelerate the 3DES application with good performance and flexibility.