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Image interpolation in firmware for 3D displayWahlstedt, Martin January 2007 (has links)
This thesis investigates possibilities to perform image interpolation on an FPGA instead of on a graphics card. The images will be used for 3D display on Setred AB’s screen and an implementation in firmware will hopefully give two major advantages over the existing rendering methods. First, an FPGA can handle big amounts of data and perform a lot of calculations in parallel. Secondly, the amount of data to transfer is drastically increased after the interpolation and with this, a higher bandwith is required to transfer the data at a high speed. By moving the interpolation as close to the projector as possible, the bandwidth requirements can be lowered. Both these points will hopefully be improved, giving a higher frame rate on the screen. The thesis consists of three major parts, where the first handles methods to increase the resolution of images. Especially nearest neighbour, bilinear and bicubic interpolation is investigated. Bilinear interpolation was considered to give a good trade off between image quality and calculation cost and was therefore implemented. The second part discusses how a number of perspectives can be interpolated from one or a few captured images and the corresponding depth or disparity maps. Two methods were tested and one was chosen for a final implementation. The last part of the thesis handles Multi Video, a method that can be used to slice the perspectives into a form that is needed for the Scanning Slit display to show them correctly. The quality of the images scaled with bilinear interpolation is satisfactory if the scale factor is kept reasonably low. The perspectives interpolated in the second part show good quality with lots of details but suffers from some empty areas. Further improvements of this function is not necessary but would increase the image quality further. An acceptable frame rate has been achieved but further improvements of the speed can be performed. The most important continuation of this thesis is to integrate the implemented parts with the existing firmware and with that enable a real test of the performance.
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Design of an FPGA-based HD-Video measurement systemLöfgren, Henrik January 2008 (has links)
In order to perform the production testing of the video quality of manufactured set-top-boxes for digital television, an FPGA-based measurement system is designed. Background on sampling and video signals are given, as well as the requirements given by Motorola. From this, a design is proposed and implemented. The demonstrator works as planned and shows good performance in regards to signal to noise ratio and differential gain. The implemented digital communication protocols, such as USB and I2C, also work as expected. The main conclusion from this thesis is that implementing video test systems using FPGA is a good approach offering many advantages compared to commercial video measurement instruments or plug-in cards for PCs.
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Hårdvarubaserade SOQPSK-algoritmer : En VHDL-implementation av algoritmer för att modulera & demodulera SOQPSK-signalerWahlgren, Max, Forsberg, Daniel January 2008 (has links)
Beroende på i vilken miljö man har tänkt att använda trådlös kommunikation behöver man hitta en modulationsteknik som passar under rådande förhållanden. I början på 1980-talet utvecklade den Amerikanska militären en modulationsteknik som kallas för Shaped BPSK (SBPSK) avsedd att tillämpas i kommunikationslänkar med satelliter. Vidareutveckling av SBPSK ledde sedan fram till en förbättrad variant kallad Shaped Offset QPSK (SOQPSK). På senare år har denna modulationsteknik börjat användas i civila tillämpningar och vidareutvecklats ytterligare för att ge den än bättre prestanda. År 2004 antogs SOQPSK som en modulationsteknik i den internationella flygplanskommunikationsstandarden, IRIG-106. Versionen av SOQPSK som antogs i IRIG-106 har flera bra egenskaper som t. ex. dess spektraltäthet. Detta gör denna typ av modulationsteknik lämpad för kommunikationslänkar med bl.a. flygplan, satelliter och rymdsonder (‘deep-space’). Målet med examensarbetet har varit att implementera algoritmer för att skicka och ta emot SOQPSK-modulerade signaler. Dessa algoritmer skulle utvecklas i VHDL för att sedan syntetiseras och programmera en FPGA. Uppgiften har givits av Syncore Technologies AB i Linköping. Arbetet har resulterat i fungerande implementationer både i mjukvara och hårdvara. Hårdvarulösningen är verifierad att klara bithastiheter upp till 30 Mbit/s. Teoretisk information om allmän modulering/demodulering och specifikt kring SOQPSK behandlas i rapporten. Uppbyggnaden av en teoretisk sändar- och mottagarmodell utformad för SOQPSK-kommunikation beskrivs också i rapporten för att ge en bättre helhetsbild av implementationen som utförts. Arbetets syfte är att ligga till grund för Syncore AB som utvecklar en kom- munikationslänk med SOQPSK-kompatibilitet.
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Nouvelle génération de systèmes de vision temps réel à grande dynamiqueLapray, Pierre-Jean 18 October 2013 (has links) (PDF)
Cette thèse s'intègre dans le cadre du projet européen EUREKA "High Dynamic Range - Low NoiseCMOS imagers", qui a pour but de développer de nouvelles approches de fabrication de capteursd'images CMOS à haute performance. L'objectif de la thèse est la conception d'un système de visiontemps réel à grande gamme dynamique (HDR). L'axe principal sera la reconstruction, en temps réelet à la cadence du capteur (60 images/sec), d'une vidéo à grande dynamique sur une architecturede calcul embarquée.La plupart des capteurs actuels produisent une image numérique qui n'est pas capable de reproduireles vraies échelles d'intensités lumineuses du monde réel. De la même manière, les écrans, impri-mantes et afficheurs courants ne permettent pas la restitution effective d'une gamme tonale étendue.L'approche envisagée dans cette thèse est la capture multiple d'images acquises avec des tempsd'exposition différents permettant de palier les limites des dispositifs actuels.Afin de concevoir un système capable de s'adapter temporellement aux conditions lumineuses,l'étude d'algorithmes dédiés à la grande dynamique, tels que les techniques d'auto exposition, dereproduction de tons, en passant par la génération de cartes de radiances est réalisée. Le nouveausystème matériel de type "smart caméra" est capable de capturer, générer et restituer du contenu àgrande dynamique dans un contexte de parallélisation et de traitement des flux vidéos en temps réel
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CAD Techniques for Robust FPGA Design Under VariabilityKumar, Akhilesh January 2010 (has links)
The imperfections in the semiconductor fabrication process and uncertainty in operating environment of VLSI circuits have emerged as critical challenges for the semiconductor industry. These are generally termed as process and environment variations, which lead to uncertainty in
performance and unreliable operation of the circuits. These problems have been
further aggravated in scaled nanometer technologies due to increased process
variations and reduced operating voltage.
Several techniques have been proposed recently for designing digital VLSI circuits
under variability. However, most of them have targeted ASICs and custom designs.
The flexibility of reconfiguration and unknown end application in FPGAs
make design under variability different for FPGAs compared to
ASICs and custom designs, and the techniques proposed for ASICs and custom designs cannot be directly applied
to FPGAs. An important design consideration is to minimize the modifications in architecture and circuit
to reduce the cost of changing the existing FPGA architecture and circuit.
The focus of this work can be divided into three principal categories, which are, improving
timing yield under process variations, improving power yield under process variations and improving the voltage profile
in the FPGA power grid.
The work on timing yield improvement proposes routing architecture enhancements along with CAD techniques to
improve the timing yield of FPGA designs. The work on power yield improvement for FPGAs selects a low power dual-Vdd FPGA design
as the baseline FPGA architecture for developing power yield enhancement techniques. It proposes CAD techniques to improve the
power yield of FPGAs. A mathematical programming technique is proposed to determine the parameters
of the buffers in the interconnect such as the sizes of the transistors and threshold voltage of the transistors, all
within constraints, such that the leakage variability is minimized under delay constraints.
Two CAD techniques are investigated and proposed to improve the supply voltage profile of
the power grids in FPGAs. The first technique is a place and route technique and the second technique
is a logic clustering technique to reduce IR-drops and spatial variation of supply voltage in the power grid.
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FPGA-based Soft Vector ProcessorsYiannacouras, Peter 23 February 2010 (has links)
FPGAs are increasingly used to implement embedded digital systems because of their low time-to-market and low costs compared to integrated circuit design, as well as their superior performance and area over a general purpose microprocessor. However, the hardware design necessary to achieve this superior performance and area is very difficult to perform causing long design times and preventing wide-spread adoption of FPGA technology. The amount of hardware design can be reduced by employing a microprocessor for less-critical computation in the system. Often this microprocessor is implemented using the FPGA reprogrammable fabric as a soft processor which can preserve the benefits of a single-chip FPGA solution without specializing the device with dedicated hard processors. Current soft processors have simple architectures that provide performance adequate for only the least-critical computations.
Our goal is to improve soft processors by scaling their performance and expanding their suitability to more critical computation. To this end we focus on the data parallelism found in many embedded applications and propose that soft processors be augmented with vector extensions to exploit this parallelism. We support this proposal through experimentation with a parameterized soft vector processor called VESPA (Vector Extended Soft Processor Architecture) which is designed, implemented, and evaluated on real FPGA hardware.
The scalability of VESPA combined with several other architectural parameters can be used to finely span a large design space and derive a custom architecture for exactly matching the needs of an application. Such customization is a key advantage for soft processors since their architectures can be easily reconfigured by the end-user. Specifically, customizations can be made to the pipeline, functional units, and memory system within VESPA. In addition, general purpose overheads can be automatically eliminated from VESPA.
Comparing VESPA to manual hardware design, we observe a 13x speed advantage for hardware over our fastest VESPA, though this is significantly less than the 500x speed advantage over scalar soft processors. The performance-per-area of VESPA is also observed to be significantly higher than a scalar soft processor suggesting that the addition of vector extensions makes more efficient use of silicon area for data parallel workloads.
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Measuring and Navigating the Gap Between FPGAs and ASICsKuon, Ian 08 March 2011 (has links)
Field-programmable gate arrays (FPGAs) have enjoyed increasing use due to their low non-recurring engineering (NRE) costs and their straightforward implementation process. However, it is recognized that they have higher per unit costs, poorer performance and increased power consumption compared to custom alternatives, such as application specific integrated circuits (ASICs). This thesis investigates the extent of this gap and it examines the trade-offs that can be made to narrow it.
The gap between 90 nm FPGAs and ASICs was measured for many benchmark circuits. For circuits that only make use of general-purpose combinational logic and flipflops, the FPGA-based implementation requires 35 times more area on average than an equivalent ASIC. Modern FPGAs also contain "hard" specific-purpose circuits such as multipliers and memories and these blocks are found to narrow the average gap to 18 for our benchmarks or, potentially, as low as 4.7 when the hard blocks are heavily used. The FPGA was found to be on average between 3.4 and 4.6 times slower than an ASIC and this gap was not influenced significantly by hard memories and multipliers. The dynamic power consumption is approximately 14 times greater on average on the FPGA than on the ASIC but hard blocks showed promise for reducing this gap. This is one of the most comprehensive analyses of the gap performed to date.
The thesis then focuses on exploring the area and delay trade-offs possible through architecture, circuit structure and transistor sizing. These trade-offs can be used to selectively narrow the FPGA to ASIC gap but past explorations have been limited in their scope as transistor sizing was typically performed manually. To address this issue, an automated transistor sizing tool for FPGAs was developed. For a range of FPGA architectures, this tool can produce designs optimized for various design objectives and the quality of these designs is comparable to past manual designs.
With this tool, the trade-off possibilities of varying both architecture and transistor-sizing were explored and it was found that there is a wide range of useful trade-offs between area and delay. This range of 2.1 X in delay and 2.0 X in area is larger than was observed in past pure architecture studies. It was found that lookup table (LUT) size was the most useful architectural parameter for enabling these trade-offs.
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Efficient Multi-ported Memories for FPGAsLaForest, Charles Eric 15 February 2010 (has links)
Multi-ported memories are challenging to implement on FPGAs since the provided block RAMs typically have only two ports. In this dissertation we present a thorough exploration of the design space of FPGA multi-ported memories by evaluating conventional solutions to this problem, and introduce a new design that efficiently combines block RAMs into multi-ported memories with arbitrary numbers of read and write ports and true random access to any memory location, while achieving significantly higher operating frequencies than conventional approaches. For example we build a 256-location, 32-bit, 12-ported (4-write, 8-read) memory that operates at 281 MHz on Altera Stratix III FPGAs while consuming an area equivalent to 3679 ALMs: a 43% speed improvement and 84% area reduction over a pure ALM implemen- tation, and a 61% speed improvement over a pure "multipumped" implementation, although the pure multipumped implementation is 7.2-fold smaller.
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Efficient Multi-ported Memories for FPGAsLaForest, Charles Eric 15 February 2010 (has links)
Multi-ported memories are challenging to implement on FPGAs since the provided block RAMs typically have only two ports. In this dissertation we present a thorough exploration of the design space of FPGA multi-ported memories by evaluating conventional solutions to this problem, and introduce a new design that efficiently combines block RAMs into multi-ported memories with arbitrary numbers of read and write ports and true random access to any memory location, while achieving significantly higher operating frequencies than conventional approaches. For example we build a 256-location, 32-bit, 12-ported (4-write, 8-read) memory that operates at 281 MHz on Altera Stratix III FPGAs while consuming an area equivalent to 3679 ALMs: a 43% speed improvement and 84% area reduction over a pure ALM implemen- tation, and a 61% speed improvement over a pure "multipumped" implementation, although the pure multipumped implementation is 7.2-fold smaller.
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Efficient Hardware Implementations For The Advanced Encryption Standard AlgorithmHammad, Issam 25 October 2010 (has links)
This thesis introduces new efficient hardware implementations for the Advanced Encryption Standard (AES) algorithm. Two main contributions are presented in this thesis, the first one is a high speed 128 bits AES encryptor, and the second one is a new 32 bits AES design. In first contribution a 128 bits loop unrolled sub-pipelined AES encryptor is presented. In this encryptor an efficient merging for the encryption process sub-steps is implemented after relocating them. The second contribution presents a 32 bits AES design. In this design, the S-BOX is implemented with internal pipelining and it is shared between the main round and the key expansion units. Also, the key expansion unit is implemented to work on the fly and in parallel with the main round unit. These designs have achieved higher FPGA (Throughput/Area) efficiency comparing to previous AES designs.
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