Multi-ported memories are challenging to implement on FPGAs since the provided block RAMs typically have only two ports. In this dissertation we present a thorough exploration of the design space of FPGA multi-ported memories by evaluating conventional solutions to this problem, and introduce a new design that efficiently combines block RAMs into multi-ported memories with arbitrary numbers of read and write ports and true random access to any memory location, while achieving significantly higher operating frequencies than conventional approaches. For example we build a 256-location, 32-bit, 12-ported (4-write, 8-read) memory that operates at 281 MHz on Altera Stratix III FPGAs while consuming an area equivalent to 3679 ALMs: a 43% speed improvement and 84% area reduction over a pure ALM implemen- tation, and a 61% speed improvement over a pure "multipumped" implementation, although the pure multipumped implementation is 7.2-fold smaller.

Multi-ported memories are challenging to implement on FPGAs since the provided block RAMs typically have only two ports. In this dissertation we present a thorough exploration of the design space of FPGA multi-ported memories by evaluating conventional solutions to this problem, and introduce a new design that efficiently combines block RAMs into multi-ported memories with arbitrary numbers of read and write ports and true random access to any memory location, while achieving significantly higher operating frequencies than conventional approaches. For example we build a 256-location, 32-bit, 12-ported (4-write, 8-read) memory that operates at 281 MHz on Altera Stratix III FPGAs while consuming an area equivalent to 3679 ALMs: a 43% speed improvement and 84% area reduction over a pure ALM implemen- tation, and a 61% speed improvement over a pure "multipumped" implementation, although the pure multipumped implementation is 7.2-fold smaller.

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The transition from the 5G to the 6G era is a pivotal juncture in contemporary wireless communication. Under such a circumstance, Digital Pre-Distortion (DPD) technology has established its significance as an effective method to linearize Power Amplifiers. However, DPD is facing a series of challenges, notably the increased bandwidth which necessitates more complex modeling techniques. This thesis focuses on the fact that the DPD requires multi-ported memories for the Look-Up-Tables to store correction coefficients, where two research questions are identified. Firstly, this thesis analyses the power, area, and delay-performance trade-offs with an increase in the number of read and write ports of Flip-Flop (FF)-based memories. Secondly, this thesis evaluates and compares the performance of the conventional FF-based multi-ported memories and algorithmic FF-based multi-ported memories. As a Master’s thesis project, this research utilizes the knowledge and practice skills expected of a Master’s student specializing in Embedded Systems. In this thesis, conventional and algorithmic multi-ported memories are implemented and evaluated after studying related works. Subsequently, an industrial Application-Specific Integrated Circuit (ASIC) design flow is executed, undergoing iterative refinements. And in the end, the conclusions are drawn based on an analysis of the software reports. The results underscore that area and power consumption exhibit linear growth alongside increased port numbers within conventional multi-ported memories. Also, the algorithmic multi-ported memory presents a promising alternative, engendering improvements across all three dimensions of delay, area, and power consumption. The implemented memories can be integrated into DPD forward path with customized port numbers in the future, offering adaptability in terms of port configuration and better performance in terms of timing, area and power. Additionally, these implemented memories stand as a valuable point of reference for engineers engaged in the development of FF-based multi-ported memories within the context of ASIC. / Övergången från den 5G- till den 6G- eran är en avgörande tidpunkt inom samtida trådlös kommunikation. Under sådana omständigheter har DPDtekniken etablerat sin betydelse som en effektiv metod för att linjärisera effektförstärkare. Dock står DPD inför en rad utmaningar, särskilt den ökade bandbredden som kräver mer komplexa modelleringstekniker. Denna avhandling fokuserar på det faktum att DPD kräver flerportsminnen för att Look-Up-Tables ska lagra korrigeringskoefficienter, där två forskningsfrågor identifieras. För det första analyserar denna avhandling effekt- , area- och fördröjningsprestanda-avvägningar med en ökning av antalet läs- och skrivportar för FF-baserade minnen. För det andra utvärderar och jämför denna avhandling prestandan hos konventionella FF-baserade multiportade minnen och algoritmiska FF-baserade multiportade minnen. Som ett masteruppsatsprojekt använder denna forskning de kunskaper och övningsfärdigheter som förväntas av en masterstudent som specialiserar sig på inbyggda system. I denna avhandling implementeras och utvärderas konventionella och algoritmiska flerportade minnen efter att ha studerat relaterade arbeten. Nästa steg är att genomföra en industriell ASIC-designflöde som genomgår iterativa förbättringar. Och till slut dras slutsatserna baserat på en analys av mjukvarurapporterna. Denna avhandling understryker att area och strömförbrukning ökar linjärt med ökade portnummer inom konventionella flerportade minnen. Å andra sidan presenterar det algoritmiska flerportade minnet ett lovande alternativ och ger förbättringar inom alla tre dimensioner av fördröjning, area och strömförbrukning. De implementerade minnena kan integreras i DPD-signalförloppet med anpassade portnummer i framtiden och erbjuda anpassningsbarhet när det gäller portkonfiguration och bättre prestanda vad gäller tid, area och ström. Dessutom utgör dessa implementerade minnen en värdefull referenspunkt för ingenjörer som är engagerade i utvecklingen av FF-baserade flerportade minnen inom ramen för ASIC.