The objective of the dissertation research is to understand the complex interaction between the algorithm and hardware aspects of symbol detection that is enhanced by lattice reduction (LR) preprocessing for wireless MIMO communication systems. The motivation for this work stems from the need to improve the bit-error-rate performance of conventional, low-complexity detectors while simultaneously exhibiting considerably reduced complexity when compared to the optimal method, maximum likelihood detection. Specifically, we first develop an understanding of the complex Lenstra-Lenstra-Lovász (CLLL) LR algorithm from a hardware perspective. This understanding leads to both algorithm modifications that reduce the required complexity and hardware architectures that are specifically optimized for the CLLL algorithm. Finally, we integrate this knowledge with an understanding of LR-aided MIMO symbol detection in a highly-correlated wireless environment, resulting in a joint LR/symbol detection algorithm that maps seamlessly to hardware. Hence, this dissertation forms the foundation for the adoption of lattice reduction algorithms in practical, high-throughput wireless MIMO communications systems.

<p>Allting började med att jag fick i uppdrag av Euromaint Industry i Skövde att konstruera en alfanumerisk display i syfte att ersätta en utgången display som inte längre nytillverkas. Jag fick i uppdrag att välja ut en modern, lämplig grafisk display och bygga ett interface mellan den nya displayen och den industriella maskin som displayen skall sitta på. Efter att ha letat hos någraelektronikleverantörer kom jag fram till att en TFT-skärm från det japanska företaget Kyocera var den som passade bäst. Skärmen hade ett VGA-liknandeinterface och min uppgift blev att sätta mig in i hur VGA fungerar. Efter att ha konstaterat att det krävdes en snabbare krets än en microcontroller för att använda VGA, var det endast en programmerbar logikkrets, en FPGA, som gällde. Denna FPGA sköter nu ensam om såväl VGA-interfacet som inläsningen av informationen från den industriella NC-maskinen.</p> / <p>Everything started when I got a task from Euromaint Industry in Skövde, Sweden, to develop an alphanumerical display that could replace an old one, which was sold out. I got a task to choose a modern, suitable, graphical display and develop an interface between the new display and the industrial machine, which the old one was connected to. I have searched for a display at some suppliers of electronic components and I have found a TFT-display from the Japanese company Kyocera. The display had an interface similar to VGA so I had to study VGA to see how it works. Then I realized that I needed a faster circuit than a microcontroller. Then I chose a programmable logic circuit, an FPGA, to control the VGA-sweep. Today the FPGA-circuit controls the whole system.</p>

In der vorliegenden Arbeit werden die Darstellungsmöglichkeiten Boolescher Funktionen durch Neuronale Netze untersucht und eine neue Art von Booleschen Neuronalen Netzen (BNN) entwickelt. Das Basiselement Boolescher Neuronaler Netze ist ein neuartiges Boolesches Neuron (BN), das im Gegensatz zum klassischen Neuron direkt mit Booleschen Signalen operiert und dafür ausschließlich Boolesche Operationen benutzt. Für das Training der BNN wurde ein sequentieller Algorithmus erarbeitet, der eine schnelle Konvergenz garantiert und somit eine kurze Trainingzeit benötigt. Dieser Trainingsalgorithmus bildet die Grundlage eines neuen geschaffenen Verfahrens zur Architektursynthese der BNN. Das entwickelte Training stellt darüber hinaus ein spezielles Dekompositionsverfahren Boolescher Funktionen dar. Neuronale Netze können sowohl in Software als auch in Hardware realisiert werden. Der sehr hohe Aufwand der Hardware-Realisierung üblicher Neuronaler Netze wurde durch die Verwendung von BN und BNN wesentlich vereinfacht. Die Anzahl erforderlicher CLBs (configurable logic blocks) zur Realisierung eines Neurons wurde um 2 Größenordnungen verringert. Ein Boolesches Neuron wird direkt auf eine einzige LUT (lookup table) abgebildet. Für diese sehr kompakte Abbildung der BNN in eine FPGA-Struktur wurde der Trainingsalgorithmus des BNN angepasst. Durch die Spezifikation der BNN mit UML-Modellen und die Anwendung der MDA-Technologie zum Hardware/Software-Codesign konnte der Syntheseaufwand für Hardware-Realisierung von BNN signifikant verringert werden.

<p> </p><p>Modern nuclear and particle physics experiments run at a very high reaction rate and are able to deliver a data rate of up to hundred GBytes/s.  This data rate is far beyond the storage and on-line analysis capability. Fortunately physicists have only interest in a very small proportion among the huge amounts of data. Therefore in order to select the interesting data and reject the background by sophisticated pattern recognition processing, it is essential to realize an efficient data acquisition and trigger system which results in a reduced data rate by several orders of magnitude. Motivated by the requirements from multiple experiment applications, we are developing a high-end reconfigurable computation platform for data acquisition and triggering. The system consists of a scalable number of compute nodes, which are fully interconnected by high-speed communication channels. Each compute node features 5 Xilinx Virtex-4 FX60 FPGAs and up to 10 GBytesDDR2 memory. A hardware/software co-design approach is proposed to develop custom applications on the platform, partitioning performance-critical calculation to the FPGA hardware fabric while leaving flexible and slow controls to the embedded CPU plus the operating system. The system is expected to be high-performance and general-purpose for various applications especially in the physics experiment domain.</p><p>As a case study, the particle track reconstruction algorithm for HADES has been developed and implemented on the computation platform in the format of processing engines. The Tracking Processing Unit (TPU) recognizes peak bins on the projection plane and reconstructs particle tracks in realtime. Implementation results demonstrate its acceptable resource utilization and the feasibility to implement the module together with the sys-tem design on the FPGA. Experimental results show that the online track reconstruction computation achieves 10.8 - 24.3 times performance acceleration per TPU module when compared to the software solution on a Xeon2.4 GHz commodity server.</p>

<p>In recent years the aviation industry is moving towards the use of programmable logic devices in airborne safety critical systems. To be able to certify the close to fail-safe functionality of these programmable devises (e.g. FPGAs) to the aviation authorities, the aviation industry uses a guideline for design assurance for airborne electronic hardware named RTCA DO-254. At the same time the PLD industry is developing ever more complex embedded system-on-chip solutions integrating more and more functionality on a single chip.</p><p>This thesis looks at the problems that rise when trying to certify system-on-chip solutions according to RTCA DO-254. Used as an example of an embedded FPGA, the Actel Fusion FPGA chip with integrated analog and digital functionality will be tested according to the verification guidance. The results show that for the time being, the examined embedded system-on-chip FPGAs can not be verified to be used in airborne safety critical systems.</p>

<p>This thesis investigates possibilities to perform image interpolation on an FPGA instead of on a graphics card. The images will be used for 3D display on Setred AB’s screen and an implementation in firmware will hopefully give two major advantages over the existing rendering methods. First, an FPGA can handle big amounts of data and perform a lot of calculations in parallel. Secondly, the amount of data to transfer is drastically increased after the interpolation and with this, a higher bandwith is required to transfer the data at a high speed. By moving the interpolation as close to the projector as possible, the bandwidth requirements can be lowered. Both these points will hopefully be improved, giving a higher frame rate on the screen.</p><p>The thesis consists of three major parts, where the first handles methods to increase the resolution of images. Especially nearest neighbour, bilinear and bicubic interpolation is investigated. Bilinear interpolation was considered to give a good trade off between image quality and calculation cost and was therefore implemented. The second part discusses how a number of perspectives can be interpolated from one or a few captured images and the corresponding depth or disparity maps. Two methods were tested and one was chosen for a final implementation. The last part of the thesis handles Multi Video, a method that can be used to slice the perspectives into a form that is needed for the Scanning Slit display to show them correctly.</p><p>The quality of the images scaled with bilinear interpolation is satisfactory if the scale factor is kept reasonably low. The perspectives interpolated in the second part show good quality with lots of details but suffers from some empty areas. Further improvements of this function is not necessary but would increase the image quality further. An acceptable frame rate has been achieved but further improvements of the speed can be performed. The most important continuation of this thesis is to integrate the implemented parts with the existing firmware and with that enable a real test of the performance.</p>

<p>At Saab Aerospace in Linköping, components for measurement systems to the fighter aircraft JAS 39 Gripen are developed. In this activity you sometimes want to record the traffic transmitted on the data busses that connects different sys-tems. This traffic on the data busses is using the military standard MIL-STD-1553. </p><p>This project has aimed to create a system for recording and sending 1553-data. The system is used on an ordinary personal computer, equipped with a recon- figurable I/O card that among others has a programmable logic circuit (FPGA). The recorded data are stored on a hard drive. The system has a graphical user interface, where the user can configure different methods of filtering the data, and other preferences. </p><p>The completed system has currently the capacity to record one channel. This works excellent and the system basically meets all the requirements stated at the start of the project. By using this system instead of the commercial available systems on the market one will get a competitive alternative. If the system where to be developed further, with more channels, it would get even more price worth. Both in case of price per channel, but also in functionality. This is because it is possible to design exactly the functions the user demands. But the current version is already fully functional and competitive compared to commercial systems.</p>

<p>In order to perform the production testing of the video quality of manufactured set-top-boxes for digital television, an FPGA-based measurement system is designed. Background on sampling and video signals are given, as well as the requirements given by Motorola. From this, a design is proposed and implemented. The demonstrator works as planned and shows good performance in regards to signal to noise ratio and differential gain. The implemented digital communication protocols, such as USB and I2C, also work as expected.</p><p>The main conclusion from this thesis is that implementing video test systems using FPGA is a good approach offering many advantages compared to commercial video measurement instruments or plug-in cards for PCs.</p>

<p>This thesis is investigating the new globally asynchronous locally synchronous (GALS) technology for integrated circuits. Different types of asynchronous wrappers are tested and a new wrapper design is presented. It also investigates the possibility to use VHDL for asynchronous simulation and synthesis. The conclusions are that the GALS technology is possible to use but that it needs new synthesis tools, because todays tools are designed for synchronous technology.</p>

<p>Beroende på i vilken miljö man har tänkt att använda trådlös kommunikation behöver man hitta en modulationsteknik som passar under rådande förhållanden. I början på 1980-talet utvecklade den Amerikanska militären en modulationsteknik som kallas för Shaped BPSK (SBPSK) avsedd att tillämpas i kommunikationslänkar med satelliter. Vidareutveckling av SBPSK ledde sedan fram till en förbättrad variant kallad Shaped Offset QPSK (SOQPSK). På senare år har denna modulationsteknik börjat användas i civila tillämpningar och vidareutvecklats ytterligare för att ge den än bättre prestanda. År 2004 antogs SOQPSK som en modulationsteknik i den internationella flygplanskommunikationsstandarden, IRIG-106. Versionen av SOQPSK som antogs i IRIG-106 har flera bra egenskaper som t. ex. dess spektraltäthet. Detta gör denna typ av modulationsteknik lämpad för kommunikationslänkar med bl.a. flygplan, satelliter och rymdsonder (‘deep-space’).</p><p>Målet med examensarbetet har varit att implementera algoritmer för att skicka och ta emot SOQPSK-modulerade signaler. Dessa algoritmer skulle utvecklas i VHDL för att sedan syntetiseras och programmera en FPGA. Uppgiften har givits av Syncore Technologies AB i Linköping.</p><p>Arbetet har resulterat i fungerande implementationer både i mjukvara och hårdvara. Hårdvarulösningen är verifierad att klara bithastiheter upp till 30 Mbit/s. Teoretisk information om allmän modulering/demodulering och specifikt kring SOQPSK behandlas i rapporten. Uppbyggnaden av en teoretisk sändar- och mottagarmodell utformad för SOQPSK-kommunikation beskrivs också i rapporten för att ge en bättre helhetsbild av implementationen som utförts.</p><p>Arbetets syfte är att ligga till grund för Syncore AB som utvecklar en kom- munikationslänk med SOQPSK-kompatibilitet.</p>