Dynamic Huffman compression algorithms operate on data-streams with a bounded symbol list. With these algorithms, the complete list of symbols must be contained in main memory or secondary storage. A horizontal format transaction database that is streaming can have a very large item list. Many nodes tax both the processing hardware primary memory size, and the processing time to dynamically maintain the tree. This research investigated Huffman compression of a transaction-streaming database with a very large symbol list, where each item in the transaction database schema’s item list is a symbol to compress. The constraint of a large symbol list is, in this research, equivalent to the constraint of a memory-limited machine. A large symbol set will result if each item in a large database item list is a symbol to compress in a database stream. In addition, database streams may have some temporal component spanning months or years. Finally, the horizontal format is the format most suited to a streaming transaction database because the transaction IDs are not known beforehand This research prototypes an algorithm that will compresses a transaction database stream. There are several advantages to the memory limited dynamic Huffman algorithm. Dynamic Huffman algorithms are single pass algorithms. In many instances a second pass over the data is not possible, such as with streaming databases. Previous dynamic Huffman algorithms are not memory limited, they are asymptotic to O(n), where n is the number of distinct item IDs. Memory is required to grow to fit the n items. The improvement of the new memory limited Dynamic Huffman algorithm is that it would have an O(k) asymptotic memory requirement; where k is the maximum number of nodes in the Huffman tree, k < n, and k is a user chosen constant. The new memory limited Dynamic Huffman algorithm compresses horizontally encoded transaction databases that do not contain long runs of 0’s or 1’s.

Afin d'accélérer ce processus de conception des systèmes embarqués, un environnement de simulation rapide et performant peut s’avérer indispensable. Pour la rendre performante, les modèles comportementaux des composants élémentaires du système doivent être capables de remplacer les éléments réels dans leurs influences et réponses à tous les phénomènes influents: perturbations, affaiblissements, retards...Nos travaux de thèse visent à contribuer à cette approche méthodologique : ils traitent le développement d’un émulateur des RCSFs. Pour ce faire deux types de simulateurs ont été étudiés:• le premier est un simulateur « software » basé sur la création de modèles comportementaux, décrits en langage VHDL-AMS.• le deuxième est un simulateur hardware basé sur la création des modèles logiques comportementaux, décrits en langage VHDL synthétisable. La simulation s’effectuera sur un composant FPGA cible. Des modifications peuvent être faites sur l’architecture de manière dynamique / To accelerate the design process of embedded systems, a fast and efficient simulation environment is needed. To make it efficient, the behavioral models of the elementary components of the system must be able to replace the real elements in their influences and responses to all the influential phenomena: disruptions, attenuation, delays...Our thesis work aims to contribute to this methodological approach: we treat the development of an emulator for WSNs. To do, two types of simulators have been studied:• The first is a software simulator based on the creation of behavioral models, described in VHDL-AMS.• The second is a hardware simulator based on the creation of behavioral logic models, described in synthesizable VHDL. The simulation will be done on an FPGA target. Changes may be made on the architecture dynamically

Indiana University-Purdue University Indianapolis (IUPUI) / The drastic increase in Internet usage demands the need for processing data in real time with higher efficiency than ever before. Symbiote Coprocessor Unit (SCU), developed by Dr. Pranav Vaidya, is a hardware accelerator which has potential of providing data processing speedup of up to 150x compared with traditional data stream processors. However, SCU implementation is very complex, fixed, and uses an outdated host interface, which limits future improvement. Mr. Tareq S. Alqaisi, an MSECE graduate from IUPUI worked on curbing these limitations. In his architecture, he used a Xilinx MicroBlaze microcontroller to reduce the complexity of SCU along with few other modifications. The objective of this study is to make SCU suitable for mass production while reducing its power consumption and delay. To accomplish this, the execution unit of SCU has been implemented in application specific integrated circuit and modules such as ACG/OCG, sequential comparator, and D-word multiplier/divider are integrated into the design. Furthermore, techniques such as operand isolation, buffer insertion, cell swapping, and cell resizing are also integrated into the system. As a result, the new design attains 67.9435 µW of dynamic power as compared to 74.0012 µW before power optimization along with a small increase in static power, 39.47 ns of clock period as opposed to 52.26 ns before time optimization.

This thesis deals with design and implementation of interconnection bus system for chips with FPGA technology. The system ensures both communication between internal components on a chip and their communication with other computer elements which are mapped to the host system memory. The buses are high-speed, full duplex and packet-oriented and their architecture is based on tree topology. The data width is configurable, individually for every bus part. Due to this feature, it is possible to build uniform hierarchical system of internal buses with different speed that interconnects differently fast components. Proposed interconnection system was implemented in VHDL language and it is utilized in the Liberouter project which is the part of CESNET research intention Programable Hardware.

This thesis deals with design and implementation of AES and DES encryption architectures for embedded systems. Architectures are implemented in VHDL language and design for FPGA technology. The proposed implementations are mapped on the Xilinx Spartan 3 technology. Both architectures are applied in simple ECB (Electronic Codebook) scheme with cache memories. A maximum throughput of design DES architecture 370 Mbps is achived with clock frequency of 104 MHz. The throughput of AES architecture at the maximum clock frequency of 118 MHz is 228 Mbps. Compared to software implementations for embedded systems, we achieve significantly higher throughput for both architectures.

Dynamic growth of computer networks encourages rapid development of network applications and services. To provide sufficient network service quality, it is important to limit some network flows based on their application protocol type. This thesis deals with the methods of network protocol identification and discusses their accuracy and suitability for multigigabit networks.  Based on the analysis, a protocol identification model was created and evaluated. The model was used for the design of hardware architecture accelerating computationally intensive operations of protocol identification.  The proposed solution is able to work on 10 Gb/s networks and export protocol information using NetFlow protocol.

Vestavený hardware je velice populární v této době. Proto jsme se rozhodli vytvořit desku s mikrokontrolérem AT91SAM9261 spolu so standartným a nestandartným hardwarem. Standartným, běžným by se dal nazvat port LAN alebo audio vstup-výstup. Nestandartným, špecialním by mohl být obvod FPGA firmy Xilinx o velikosti 200k. Toto dovoluje využít zažízení v oblastech, kde výpočetní síla obyčejnýho CPU již není dostačující.

The aim of this thesis was to design and implement PCI Express Bridge. The main purpose of this unit is to help application engineers who develop various FPGA based accelerators. The implemented unit transforms complex PCI Express based system bus interface to more common and scalable interface of internal bus for on-chip components interconnection. This allows engineers to focus on the development of their target applications, not on a complicated communication protocol. The unit was implemented in the VHDL language, synthesized for Virtex-5 based FPGAs as well as completely tested on ML555 and COMBOv2 cards. The acquired results show that the component reaches the throughput of 7 Gb/s, which is the theoretical limitation of underlying protocols.

Aim of this master's thesis is the creation of serial communication interface for FITkit. This serial interface is a full duplex industrial bus based on 20mA loop circuit and it should allow connection of two FITkits by RS-485. Aim of this paper is to design simple software allowing communication of two FITkits and to secure this communication on RS-485 link against interference or transfer errors.

This thesis deals with the design and implementation of an FPGA-based platform for rapid development of network applications for the COMBO cards family. The proposed platform includes a generic data transfer protocol - FrameLink, a set of tools for FrameLink manipulation, network interface blocks for 1 Gigabit Ethernet, high-speed connection to the software layer via PCI, PCI-X or PCI Express bus and a set of IP cores for network traffic analysis and processing. The benefits of the proposed platform are demonstrated on design and implementation of a network interface card, hardware firewall and exporter of unified packet headers.