This thesis introduces a new way to characterize the dynamic SEU cross section of an FPGA design in terms of its persistent and non-persistent components. An SEU in the persistent cross section results in a permanent interruption of service until reset. An SEU in the non-persistent cross section causes a temporary interruption of service, but in some cases this interruption may be tolerated. Techniques for measuring these cross sections are introduced. These cross sections can be measured and characterized for an arbitrary FPGA design. Furthermore, circuit components in the non-persistent and persistent cross section can statically be determined. Functional error mitigation techniques can leverage this identification to improve the reliability of some applications at lower costs by focusing mitigation on just the persistent cross section. The reliability of a practical signal processing application in use at Los Alamos National Laboratory was improved by nearly two orders of magnitude at a theoretical savings of over 53% over traditional comprehensive mitigation techniques such as full TMR.

Unmanned vehicles (UVs) are seeing more widespread use in military, scientific, and civil sectors in recent years. These UVs range from unmanned air and ground vehicles to surface and underwater vehicles. Each of these different UVs has its own inherent strengths and weaknesses, from payload to freedom of movement. Research in this field is growing primarily because of the National Defense Act of 2001 mandating that one-third of all military vehicles be unmanned by 2015. Research using small UVs, in particular, is a growing because small UVs can go places that may be too dangerous for humans. Because of the limitations inherent in small UVs, including power consumption and payload, the selection of light weight and low power sensors and processors becomes critical. Low power CMOS cameras and real-time vision processing algorithms can provide fast and reliable information to the UVs. These vision algorithms often require computational power that limits their use in traditional general purpose processors using conventional software. The latest developments in field programmable gate arrays (FPGAs) provide an alternative for hardware and software co-design of complicated real-time vision algorithms. By tracking features from one frame to another, it becomes possible to perform many different high-level vision tasks, including object tracking and following. This thesis describes a vision guidance system for unmanned vehicles in general and the FPGA hardware implementation that operates vision tasks in real-time. This guidance system uses an object following algorithm to provide information that allows the UV to follow a target. The heart of the object following algorithm is real-time rank transform, which transforms the image into a more robust image that maintains the edges found in the original image. A minimum sum of absolute differences algorithm is used to determine the best correlation between frames, and the output of this correlation is used to update the tracking of the moving target. Control code can use this information to move the UV in pursuit of a moving target such as another vehicle.

Radio astronomy is the discipline dedicated to the study of celestial emissions in the radio band from a few MHz to 300 GHz. In recent years, spurious emissions from man-made devices that operate at these frequencies have made detection of astronomical signals difficult. These harmful RF transmissions are called radio frequency interference (RFI). One strategy to remove RFI is to apply spatial filtering using an array antenna. This thesis documents the development of a high-speed data acquisition system used to record data from 7- and 19-element phased array feeds. The system supports synchronous sampling over all channels and streams data to disk allowing spatial filtering to be applied in post-processing. The development of a time blanking RFI mitigation system was also developed as part of this thesis. Time blanking is a strategy to remove radar interference by blanking the time intervals corrupted by radar transmissions. The two blanking strategies are time window blanking and detected pulse blanking. This thesis documents the design and implementation of a detected pulse blanking system built using FPGAs. The system employs complex signal processing techniques to detect and excise radar transmissions in real time. This FPGA RFI mitigation system is the first to use a matched filter in pulse detection. Successful radio frequency interference mitigation is demonstrated by removing simulated radar interference from a sinusoidal tone.

Motion is one of the most important features describing an image sequence. Motion estimation has been widely applied in structure from motion, vision-based navigation and many other fields. However, real-time motion estimation remains a challenge because of its high computational expense. The traditional CPU-based scheme cannot satisfy the power, size and computation requirements in many applications. With the availability of new parallel architectures such as FPGAs and GPUs, applying these new technologies to computer vision tasks such as motion estimation has been an active research field in recent years. In this dissertation, FPGAs have been applied to real-time motion estimation for their outstanding properties in computation power, size, power consumption and reconfigurability. It is believed in this dissertation that simply migrating the software-based algorithms and mapping them to a specific architecture is not enough to achieve good performance. Accuracy is usually compromised as the cost of migration. Improvement and optimization at the algorithm level are critical to performance. To improve motion estimation on the FPGA platform and prove the effectiveness of the method, three main efforts have been made in the dissertation. First, a lightweight tensor-based algorithm has been designed which can be implemented in a fully pipelined structure. Key factors determining the algorithm performance are analyzed from the simulation results. Second, an improved algorithm is then developed based on the analyses of the first algorithm. This algorithm applies a ridge estimator and temporal smoothing in order to improve the accuracy. A structure composed of two pipelines is designed to accommodate the new algorithm while using reasonable hardware resources. Third, a hardware friendly algorithm is developed to analyze the optical flow field and detect obstacles for unmanned ground vehicle applications. The motion component is de-rotated, de-translated and postprocessed to detect obstacles. All these steps can be efficiently implemented in FPGAs. The characteristics of the FPGA architecture are taken into account in all development processes of these three algorithms. This dissertation also discusses some important perspectives for FPGA-based design in different chapters. These perspectives include software simulation and optimization at the algorithm development stage, hardware simulation and test bench design at the hardware development stage. They are important and particular for the development of FPGA-based computer vision algorithms. The experimental results have shown that the proposed motion estimation module can perform in real-time and achieve over 50% improvement in the motion estimation accuracy compared to the previous work in the literature. The results also show that the motion field can be reliably applied to obstacle detection tasks.

Three new and efficient carrier frequency offset estimators are created for the case of disjoint pilot symbol blocks. The estimators are efficient in both a statistical sense and a computational sense. They are formulated to reduce computational cost for use in real-time applications, such as FPGA (field programmable gate array) devices. A reduced cost maximum likelihood (ML) frequency estimator is described. It is a generalization of the approximate ML estimator for a single block of pilot symbols. A number of recent ML estimation techniques are integrated with the purpose of reducing the computational cost while preserving estimation performance. The estimator incorporates multirate signal processing methods, FFT periodogram searches, and directed periodogram searches. The subsequent relationships between FFT lengths, resampling rates, and search iterations is established. The proposed estimator exhibits very good accuracy, operating range, and a low SNR threshold, and has low cost. A data-aided frequency estimator based on the measurement of phase increments, is also derived. It has extremely low cost, but a high SNR threshold. However, its formulation is such that a careful analysis of the range error problem may be performed. From this analysis certain conclusions are made about proper pilot symbol organization, and these conclusions are applicable to other frequency estimators. The third estimator is a generalization of the autocorrelation frequency estimation technique. The generalizations are needed to account for the spacings between the pilot blocks. A novel iterative approach, incorporating a Kalman filter, is used to improve operating range. It is shown that the autocorrelation frequency estimator exhibits good accuracy while maintaining a useful operating range. Real-time architectures are described for the ML and autocorrelation frequency estimators using disjoint pilot blocks. The computational cost and estimation performance of the proposed estimators are analyzed and it is shown that they give estimation performance near to theoretical limits, while preserving wide operating range. We see that the autocorrelation estimator is appropriate for small numbers of pilot symbols, while the ML estimator is appropriate for large numbers of pilot symbols. The new frequency estimators are the first to be derived (for the case of disjoint blocks of pilot symbols) such that computational cost is kept low, while still achieving high accuracy, a wide operating range, and low SNR thresholds.

Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems that employ configuration scrubbing, majority voters are needed in all feedback paths to ensure proper synchronization between the TMR replicates. Synchronization voters, however, consume additional resources and impact system timing. This work introduces and contrasts seven algorithms for inserting synchronization voters while automatically performing TMR. The area cost and timing impact of each algorithm on a number of circuit benchmarks is reported. The work demonstrates that one of the algorithms provides the best overall timing performance results with an average 8.5% increase in critical path length over a triplicated design without voters and a 29.6% area increase. Another algorithm provides far better area results (an average 3.4% area increase over a triplicated design without voters) at a slightly higher timing cost (an average 14.9% increase in critical path length over a triplicated design without voters). In addition, this work demonstrates that restricting synchronization voter locations to flip-flop output nets is an effective heuristic for minimizing the timing performance impact of synchronization voter insertion.

This work presents on-orbit experiments conducted to validate SEU mitigation and detection techniques on FPGA devices and to measure SEU rates in FPGAs and SDRAM. These experiments were designed for the Cibola Flight Experiment Satellite (CFESat), which is an operational technology pathfinder satellite built around 9 Xilinx Virtex FPGAs and developed at Los Alamos National Laboratory. The on-orbit validation experiments described in this work have operated for over four thousand FPGA device days and have validated a variety of SEU mitigation and detection techniques including triple modular redundancy, duplication with compare, reduced precision redundancy, and SDRAM and FPGA block memory scrubbing. Regional SEU rates and the change in CFE's SEU rate over time show the measurable, expected effects of the South Atlantic Anomaly and the cycle of solar activity on CFE's SEU rates. The results of the on-orbit experiments developed for this work demonstrate that FPGA devices can be used to provide reliable, high-performance processing to space applications when proper SEU mitigation strategies are applied to the designs implemented on the FPGAs.

With the advent of software-defined radio, many radio applications have and are currently being designed for FPGAs, due to their high performance and reconfigurability. Invariably, "legacy" waveforms, such as FM, will need to be supported in such systems. A challenge that comes with programming FPGAs is the increased design and implementation time over conventional software programming. In this thesis, three FM demodulator techniques are implemented and compared in an FPGA. Two techniques are found to have similar SNR performance while having very different FPGA implementation characteristics. Library based design is explored for demodulators to increase FPGA design productivity. A block library is created and verified by use in tested demodulator designs. Two design tools that aim to increase design productivity in FPGAs, Ogre and HMFlow, are also examined and used to implement FM demodulators in a PCM/FM receiver design. Ogre leverages the demodulator block library, along with accompanying metadata, to decrease design time significantly. Design performance is not sacrificed when using Ogre. HMFlow, which relies on finer-grained blocks, reuses block implementation data to speed up implementation of the full design. The implementation of the HMFlow demodulator design is sped up by 3x but, when compared with the standard flow, produces an implementation with a reduced maximum clock rate (about 1/2) and with slightly more resources (about 6%). When comparing Ogre with HMFlow, the coarser-grained blocks of Ogre provide a more efficient design experience than that of HMFlow.

When designing custom hardware to implement signal processing algorithms, it is important to select bitwidths that meet the minimum error requirements while minimizing implementation area. Larger bitwidths reduce error, but increase area, while selecting smaller bitwidths does the opposite. Finding the set of bitwidths that produces the smallest area that still meets the error requirements has been shown to be NP-hard. To address this problem, many heuristics have been developed. Unfortunately, they are not always well documented and do not have available source code. It is also di cult to know which algorithm to try to use. This thesis addresses these challenges in several ways. It provides the necessary background information to understand bitwidth optimization algorithms, as well as a survey of the existing literature. It also presents a new framework called Bitwidth Analysis Tool (BAT) built on the open source Ptolemy tool. This framework is designed to help implement and compare bitwidth optimization algorithms. Some existing algorithms are implemented within this new framework, and compared with each other on a variety of benchmarks. The comparison results verify that because the tested algorithms are heuristics, no single algorithm gives the best results in all cases. It is therefore important to test a variety of algorithms to try to find the best answer. The results also show existing algorithms and error models provide a good starting point, but existing error models do not yet provide sufficiently tight bounds to be useful in large complex systems.

Space-based computing applications often demand reliable, high-bandwidth communication systems. FPGAs with Mulit-Gigabit Transceivers (MGTs) provide an effective platform for such systems, but it is important that system designers understand the possible susceptibilities MGTs present to the system. Previous work has provided a foundation for understanding the susceptibility of raw FPGA MGTs but has fallen short of testing MGTs as part of a larger system. This work focuses on answering the questions MGT system designers need to know in order to build a reliable space-based MGT system. Two radiation tests were performed with a test architecture built on the Aurora protocol. These tests were specifically designed to discover system susceptibilities, and effective mechanisms for upset detection, recovery, and recovery detection. Test results reveal that the Aurora protocol serves as an effective basis for simple point-to-point communication for space-based systems but that some additional logic is necessary for high reliability. Particularly, additional upset detection and recovery mechanisms are necessary as well as additional status indicators. These additions are minimal, however, and not all are necessary depending on system requirements. The most susceptible part of the MGT system is the MGT tile components on the RX data path. Upsets to these components most often results in data corruption only and do not affect system operation or disrupt the communication link. Most other upsets which do disrupt normal system operation can be recovered automatically by the Aurora protocol with built-in mechanisms. Only 1% of observed events in testing required additional recovery mechanisms not supplied by Aurora. In addition to test data results, this work also provides suggestions for system designers based on various system requirements and a proposed MGT system design based on the Aurora protocol. The proposed system serves as an example to illustrate how test data can be used to guide the system design and determine system availability. With this knowledge designers are able to build reliable MGT systems for a variety of space-based systems.