Machine Learning is growing in popularity and spreading across different fields for various applications. Due to this trend, machine learning algorithms use different hardware platforms and are being experimented to obtain high test accuracy and throughput. FPGAs are well-suited hardware platform for machine learning because of its re-programmability and lower power consumption. Programming using FPGAs for machine learning algorithms requires substantial engineering time and effort compared to software implementation. We propose a software assisted design flow to program FPGA for machine learning algorithms using our hardware library. The hardware library is highly parameterized and it accommodates Tree Classifiers. As of now, our library consists of the components required to implement decision trees and random forests. The whole automation is wrapped around using a python script which takes you from the first step of having a dataset and design choices to the last step of having a hardware descriptive code for the trained machine learning model.

Wireless communication systems utilize the wireless medium to perform over-the-air (OTA) data transfer. There are many factors that can impact the quality of wireless communications, such as medium imperfection, interfering environment, mismatch of transceivers, etc. To mitigate these problems and improve the quality of service (QoS), this research study is conducted on three important topics including synchronization techniques, impairment estimation theory and techniques, and interference alignment techniques. In this thesis, it firstly present a dual link algorithm to align and manage the interference of multiple-input and multiple-output (MIMO) networks. A field-programmable gate array (FPGA) prototype is designed for software defined radio (SDR) platforms. As one of the key components, a hardware efficient architecture is proposed for the implementation of singular value decomposition (SVD). Secondly, it proposes a maximum-likelihood (ML) based synchronization approach for carrier frequency synchronization for MIMO systems. The algorithm is also implemented on FPGA for real-time performance evaluation. Finally, as an exemplary study of machine learning techniques for wireless communications, a neural network (NN) based estimator is proposed to perform coarse frequency offset estimations for MIMO systems. The proposed NN based estimator can accommodate various channel models and the results show promising performance in terms of accuracy and estimation range. In summary, this thesis provides a comprehensive study on interference alignment, carrier synchronization, and impairment estimation using different approaches. Efficient hardware implementations for the key algorithms are also presented.

abstract: Convolutional Neural Network (CNN) has achieved state-of-the-art performance in numerous applications like computer vision, natural language processing, robotics etc. The advancement of High-Performance Computing systems equipped with dedicated hardware accelerators has also paved the way towards the success of compute intensive CNNs. Graphics Processing Units (GPUs), with massive processing capability, have been of general interest for the acceleration of CNNs. Recently, Field Programmable Gate Arrays (FPGAs) have been promising in CNN acceleration since they offer high performance while also being re-configurable to support the evolution of CNNs. This work focuses on a design methodology to accelerate CNNs on FPGA with low inference latency and high-throughput which are crucial for scenarios like self-driving cars, video surveillance etc. It also includes optimizations which reduce the resource utilization by a large margin with a small degradation in performance thus making the design suitable for low-end FPGA devices as well. FPGA accelerators often suffer due to the limited main memory bandwidth. Also, highly parallel designs with large resource utilization often end up achieving low operating frequency due to poor routing. This work employs data fetch and buffer mechanisms, designed specifically for the memory access pattern of CNNs, that overlap computation with memory access. This work proposes a novel arrangement of the systolic processing element array to achieve high frequency and consume less resources than the existing works. Also, support has been extended to more complicated CNNs to do video processing. On Intel Arria 10 GX1150, the design operates at a frequency as high as 258MHz and performs single inference of VGG-16 and C3D in 23.5ms and 45.6ms respectively. For VGG-16 and C3D the design offers a throughput of 66.1 and 23.98 inferences/s respectively. This design can outperform other FPGA 2D CNN accelerators by up to 9.7 times and 3D CNN accelerators by up to 2.7 times. / Dissertation/Thesis / Masters Thesis Computer Science 2020

The popularity of field-programmable gate arrays (FPGA) has grown in recent years due to their potential performance advantages over sequential software, and as a prototyping platform for application-specific integrated circuits (ASIC). Vendors such as Xilinx offer automated tool suites that can be used to program FPGAs based on a RTL description. These tool suites are sufficient forgeneral users, but they usually don't provide the opportunity to integrate custom computer-aideddesign (CAD) tools into the regular design flow. Xilinx first offered this capability in their ISE tool suite with the Xilinx Design Language (XDL). Using XDL, a Xilinx design could be extracted from the regular CAD flow, run through an external tool, and injected back into the flow. Research tools targeting commercial FPGAs have most commonly been based on XDL. Vivado (Xilinx's newest tool suite) no longer supports XDL, preventing similar tools from being created for next-generation devices. Instead, Vivado includes a Tcl interface that exposes Xilinx's internal design and device data structures. Considerable challenges still remain to users attempting to leverage this Tcl interface to develop external CAD tools. This thesis presents the Vivado Design Interface (VDI), a set of file formats and Tcl functions that address the challenges of exporting and importing designs to and from Vivado. To demonstrate its use, VDI has been integrated with RapidSmith2, an external FPGA CAD framework. To the best of our knowledge this work is the first successful attempt to provide an opensource tool-flow that can export designs from Vivado, manipulate them with external CAD tools, and re-import an equivalent representation back into Vivado.

SRAM-based Field Programmable Gate Arrays (FPGAs) must be programmed with configuration data every time they are powered on. In addition to initially programming an FPGA, there are many other applications that require access to FPGA configuration memory such as partial reconfiguration, fault injection, and memory scrubbing. This thesis describes a system that provides high-speed, programmable configuration management for Xilinx FPGAs through external interfaces. This system is an improvement upon the JTAG Configuration Manager (JCM) previously created at BYU. The JCM consists of a custom I/O board paired with a MicroZed development board which includes a Xilinx ZYNQ SoC. This platform is used to implement a flexible configuration management system that can communicate with Xilinx FPGAs at high speeds using the JTAG and SelectMAP interfaces.The improved system described in this thesis increases the maximum data transfer rate of the JCM's JTAG and SelectMAP interfaces and dramatically decreases the processor utilization of user programs running on the JCM. This is accomplished by incorporating a Direct Memory Access (DMA) engine and interrupts into the system. In addition to faster data rates, these changes and the decrease in processor utilization also allow the JCM to manage up to eight JTAG chains simultaneously with the use of a special I/O card.

This thesis presents a novel work on hardware realization of symmetric image encryption utilizing chaos based continuous systems as pseudo random number generators. Digital implementation of chaotic systems results in serious degradations in the dynamics of the system. Such defects are illuminated through a new technique of generalized post proceeding with very low hardware cost. The thesis further discusses two encryption algorithms designed and implemented as a block cipher and a stream cipher. The security of both systems is thoroughly analyzed and the performance is compared with other reported systems showing a superior results. Both systems are realized on Xilinx Vetrix-4 FPGA with a hardware and throughput performance surpassing known encryption systems.

Cílem práce je návrh univerzální řídicí jednotky pro CubeSat založené na obvodu FPGA. Taková jednotka doposud nebyla komerčně dostupná a navržená jednotka má tak dobrý potenciál zaplnit příslušné místo na trhu komponent pro CubeSat. Celá jednotka je navržena z komerčně dostupných komponent. Návrh jednotky je proveden tak, aby umožnil její funkci ve vesmírném prostředí. Stav konfigurace FPGA je pravidelně kontrolován a v případě zjištěné chyby dochází automaticky k rekonfiguraci FPGA a návratu jednotky do výchozího stavu. Jednotka obsahuje sadu senzorů, které monitorují její stav a v případě potřeby je možné na základě jejich výstupů provést opatření z hlediska ochrany funkce jednotky. Dvě paměti MRAM umožňují uložení tovární a uživatelské konfigurace FPGA, mezi kterými dochází k automatickému přepnutí na základě korektnosti uživatelské konfigurace.

This master's thesis is focused on the design of a highspeed aquizition system which is based on FPGA and a highspeed AD converter with modern JESD204B interface. Considering the requirements, such as high samplig rate, the current range of available devices is limited. Therefore the market overview of the modern IC and modules was made. The resulting design is based on available modules, so the rached sampling rate is up to 5 GSa/s with 12bits resolution. Data from measurement are send to PC via Ethernet which uses lwIp stack and TEMAC core on Microblaze proccessor.

The presented thesis deals with the design of a system capable of tracking the moving objects. The output of the thesis is the prototype layout of the device. Facility will be physically placed between the camera and the tripod in the dissertation and tested in real conditions. The role of this system is to automatically rolling the camera up the selected moving object.

This diploma thesis deals with the problem of high-speed communication security which leads to the usage of hardware accelerators, in this case high-speed FPGA NICs. Work with simplification of development of FPGA hardware accelerator applications using the P4 to VHDL compiler. Describes extension of compiler of cryptographic external objects support. Teoretical introduction of the thesis explains basics of P4 language and used technologies. Describes mapping of external objects to P4 pipeline and therefore to FPGA chip. Subsequently deals with cryptographic external object, compatible wrapper implementation and verification of design. Last part describes implementation and compiler extension, cryptographic external object support and summarizes reached goals.