This work describes a novel approach of HW/SW codesign on the Xilinx Zynq and similar platforms. It deals with interconnections between the Processing System (ARM Cortex-A9 MPCore) and the Programmable Logic (FPGA) to find an abstract and universal way to develop applications that are partially offloaded into the programmable hardware and that run in the Linux operating system. For that purpose a framework for HW/SW codesign on the Zynq and similar platforms is designed. No such framework is currently available.

Eight-bit computer ZX Spectrum has been created 30 years ago. It was extremely popular in its time and it has many fans till now, which still developing new application and games. There are also many new hardware extensions like IDE HDD driver, SD/MMC memory driver etc. The aim of this thesis is the design and develop of ZX Spectrum emulator, which will be based on modern PFGA technology and it will use modern periphery like VGA monitor, SD/MMC memory cards etc.

VLIW processors are parallel computing devices that are used in embedded devices as well as in servers. My thesis contains description of this architecture. It is aimed at making and subsequently implementing design of custom general-purpose VLIW processor with wide range of configurable parameters. Operational implementation of such processor in VHDL which can be tested on FITkit platform is an integral part.

The aim of this thesis is to draft and implement high-speed encryptor of network trafic with throughput 10Gb/s in one way. It has been implementated for FPGA Xilinx Virtex5vlx155t placed on card COMBOv2-LXT. The encryption is based on AES algorithm using 128 bit key length. The security protokol is ESP in version for protokol IPv4. Design is fully synthesizable with tool Xilinx ISE 11.3, however it is not tested on real hardware. Tests in simulation works fine.

This work deals with modernization of information LED panels. It mainly focuses on utilizing input HDMI interface into FPGA, which controls modular LED displays, but also on ensuring professional functions such as communication with control unit, thermal security and detection of faulty LED.

The submitted thesis is concerned with a design of the multiplicator of memory cards. The basic focus of this thesis is the analysis of individual system components and adjustment of the existing arrangement. The analysis describes the existing arrangement of the multiplicator and deals with the potential of individual components. Adjustment of the existing arrangement includes definitions and processes of the individual multiplicator components design to the achievement of optimal performance. Operating of the multiplicator is fully controlled by a PC.

This work describes an extension of the Microprobe functionality for detection and filtering of application protocols. The Microprobe is an embedded system designed for monitoring network links at speed 1 Gb/s without loosing any packets. The detection of application protocols requires using of computationally expensive operations, especially string lookup (usually based on regular expressions). Based on the study of several protocols (SMTP, POP3, FTP, SIP) a draft of a new architecture has been created. The new architecture splits this functionality between programmable logic FPGA and processor. The FPGA performs preprocessing of network traffic consisting of a lookup for user identifiers and protocol-specific patterns. The processor verifies that it is the requested communication. The processor does not need to process the entire network traffic but only the part pre-filtered in the FPGA. The software part is extended by a module for the analysis of SMTP which allows processing of more than 5,000 network flows per second. Support for other protocols can be added by an extension of the software part.

The goal of this thesis is how to implement the two different types of the electric alternate motors in ZYNQ-7000 device for MIL real-time simulation purposes. The chosen types of motors are BLDC motor and AC induction motor. Mathematics models of these motor, the necessary changes for implementation purposes and the way how the models were implemented in ZYNQ-7000 device are described in this work. Three different experimental MIL simulation, using these motors ae described at the end of this thesis.

Embedded multi-core systems are implemented as systems-on-chip that rely on packet store-and-forward networks-on-chip for communications. These systems do not use buses nor global clock. Instead routers are used to move data between the cores and each core uses its own local clock. This implies concurrent asynchronous computing. Implementing algorithms in such systems is very much facilitated using dataflow concepts. In this work, we propose a methodology for implementing algorithms on dataflow platforms. The methodology can be applied to multi-threaded, multi-core platforms or a combination of these platforms as well. This methodology is based on a novel dataflow graph representation of the algorithm. We applied the proposed methodology to obtain a novel dataflow multi-core computing model for the secure hash algorithm-3. The resulting hardware was implemented in FPGA to verify the performance parameters. The proposed model of computation has advantages such as flexible I/O timing in term of scheduling policy, execution of tasks as soon as possible, and self-timed event-driven system. In other words, I/O timing and correctness of algorithm evaluation are dissociated in this work. The main advantage of this proposal is the ability to dynamically obfuscate algorithm evaluation to thwart side-channel attacks without having to redesign the system. This has important implications for cryptographic applications. Also, the dissertation proposes four countermeasure techniques against side-channel attacks for SHA-3 hashing. The countermeasure techniques are based on choosing stochastic or deterministic input data scheduling strategies. Extensive simulations of the SHA-3 algorithm and the proposed countermeasures approaches were performed using object-oriented MATLAB models to verify and validate the effectiveness of the techniques. The design immunity for the proposed countermeasures is assessed. / Graduate / 2020-11-19

This work reviews the development frameworks available for the Altera System-On-Chip solutions. These solutions are then compared to solutions available on the Xilinx platform. The RSoC Framework is then presented as an advantageous alternative for the vendor's solutions. This framework is currently available for the Xilinx Zynq platform. Furthermore the work assess the key differences between Xilinx Zynq and Altera Cyclone V SoC platforms and proposes the solution to port the framework to Altera platform. The design and implementation of then RSoC Framework port to Altera Cyclone V SoC is then discussed. Finally the work evaluates the performance of the ported system on the new platform.