The work deals with the available options of security devices for basements, design and implementation of its own security equipment. An FPGA chip from Xilinx was used as a device control. The device also contains a GSM module for sending information via SMS about space violation. Intrusion signaling can also be signaled by a siren. Intrusion detection is performed using a door and motion sensor. The whole device is powered by a battery, but there is also the possibility of mains power.

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An intelligent camera includes a processor, which can extract information from images without the need for an external processing unit, and interface devices used to make the results available to other devices. This paper describes the intelligent camera design and implementation into the Field Programmable Gate Array (FPGA). The implemented architecture contains a camera controller, a memory controller, an IIC controller, a VGA controller, and an execution unit. The camera controller communicates with a CMOS chip. The memory controller communicates with a DDR SDRAM memory. The IIC controller is the interface between a PLB bus and an IIC bus. The VGA controller takes data from the memory and transform them into the VGA format (640x480, 60 Hz). The execution unit extracts the image data from the memory. These data are processed by hardware pixel by pixel, which results in a modified image. The camera units has been implemented in the VHDL and Verilog languages.

This work explicates a simple GPS receiver intended for laboratory demonsration of DSSS signal demodulation and apparent distance measurement. The receiver will be able to seek for individual sattelite signals, measure their shift against local oscillator, demodulate navigational data, display information on LCD and communicate with PC via USB.

Fading channel is a communication channel that experiences different interference and fading due to multi-path signal propagation. The fading channel is designed by the finite impulse response filter with the time-varying impulse characteristic. The realisation of this filtr is based on the TDL (Tapped Delay Line) model, which simulate signal delay and signal attenuation in each branch. The aim of this thesis is to create the VHDL design of selected fading channel simulator and its description for hardware implementation into the FPGA.

This thesis describes reconstruction of scene which is scan trough two cameras. There are described methods of calibration of cameras system, methods for finding the corners and methods for finding correspondences. Corners are searched by FAST detector and for search correspondences are used normalized cross correlation. In the framework of 3D reconstruction is implemented rectification. The final shape is saved to VRML format. In the thesis are described parallelization options. The calculation of the correlation is optimized for multiprocessors CPU and there are designed implementations of algorithm to GPU and FPGA too.

This thesis deals with utilizing C2H technique for implementation algorithm on FPGA. Several structures of digital filters FIR and IIR are implemented within this work with usage of C2H. For such a comparison is in terms of FPGA resources utilized, the maximum frequency, latency, complexity of implementation and acceleration obtained to Nios II processor itself. Example for image processing using local operators implemented using C2h is also created to display the result on the LCD.

The theme of this thesis is presentation of the CompactRIO platform by National Instruments with its range of hardware and the possibility of using this platform for the frequency measurement of analog signals. The result of this thesis is software equipment for this device focusing on the frequency measurement of analog signals and experimental verification of posibilities of a specific configuration of this platform in the range of measurable frequencies.

The goal of this project is to design a signal and data logger, which captures analog and digital signals with very long record time. The device supports multichannel complex triggering, a real-time oscilloscope-like mode and an offline mode for analyzing of previously sampled data. This project contains detailed analysis of the topic, description of hardware and software solutions and used methods. The thesis also contains verification tests and measurements. This device will be mainly used for hardware debugging of microprocessor based applications.

Thesis deals with the challenges in the field of BLDC motors control with the utilization of Field Programmable Gate Arrays (FPGA). Using the modular dSPACE hardware with the FPGA board, these issues are solved: sensored and sensorless control, real-time simulation of BLDC motor and control of BLDC motor in degraded mode. FPGA design is made using the System Generator for DSP from Xilinx. The side effect of work is to show that with the expansion of high-level tools for FPGA design, the implementation of algorithms for FPGA is relatively quick and efficient and does not require years of experience and big knowledge of field programmable gate arrays. The implementation of algorithms on FPGA instead of processors brings many advantages, in the first place the high speed processing and low latency.