Companies and authorities of today often handle large amount of data, not unusually with a restricted content which should be kept secret from outsiders. One way of accomplish this is to encrypt stored data in real time. For this a hardware solution is ideal since it can be independent, fast enough, and easily added to already existing systems. This report is a starting point to achieve this with two of the most common mass storage standards SATA and SCSI in focus. It is based on the task to develop a FPGA based SATA controller and investigate the possibility to ”speak” SCSI with SATA devices. The working process has involved theoretical studies, system design, test driven development using simulations and hardware tests and technical investigation. The thesis resulted in a SCSI-to-SATA translation investigation pointing out difficulties and presenting a translation model. A SATA host was also implemented in VHDL on a Virtex-5 FPGA that can execute a number of SATA commands on different devices. Simulations performed shows that the total latency reaches one μs/32 bits in the SATA host and that should not be much of a problem for most applications in a possible bridge solution.

The target of this master thesis is to evaluate the Image Warping technique and propose a possible design for an implementation in FPGA. The Image Warping is widely used in the image processing for image correction and rectification. A DSP is a usual choice for implantation of the image processing algorithms, but to decrease a cost of the target system it was proposed to use an FPGA for implementation. In this work a different Image Warping methods was evaluated in terms of performance, produced image quality, complexity and design size. Also, considering that it is not only Image Warping algorithm which will be implemented on the target system, it was important to estimate a possible memory bandwidth used by the proposed design. The evaluation was done by implemented a C-model of the proposed design with a finite datapath to simulate hardware implementation as close as possible.

Here at ISY research is performed on network processors. In order to evaluate the processors there is a need to have full control of every aspect of the transmission. This is not the case if you use a proprietary technology. Therefore the need for a well documented gigabit Ethernet network interface has emerged. The purpose of this thesis work has been to design and implement an open source gigabit Ethernet controller in a FPGA together with a device driver for the Linux operating system Implementation has been done in Verilog for the hardware part and the software was developed in C. We have implemented a fully functional gigabit Ethernet interface onto a Xilinx Virtex II-1500 FPGA together with a Linux device driver. The design uses approximately 7200 LUTs and 48 block RAMs including the opencores PCI bridge.

This design accomplished Tic-Tac-Toe game on Xilinx Spartan-IIE FPGA platformin VHDL. Firstly, designing the circuits and wiring on experiment board. Secondly,designing the algorithm and programming it in Active-HDL. Thirdly, synthesizingit in Synplicity Synplify Pro and then implementing it in Xilinx ISE developingsuite. Finally download it onto FPGA to run it. This design allows two players to play Tic-Tac-Toe game on the experiment board.Pressing the key, the corresponding LED will be light up to represent thechessman. There are two LEDs indicate whose turn next is. If the grid one wantsto place chessman has been taken up, then LCD will alarm it and ask the playerto replace it. The first player who forms 3 chessmen in a row, column or diagonalwins, LCD will display it and the three LEDs in the winning line will blink. If nobody wins after filling the whole chessboard, then LCD displays draw.

The rapidly increasing capabilities of digital electronics have increased the demand of Software Defined Radio (SDR), which were not possible in the special purpose hardware. These enhanced capabilities come at the cost of time due to complex operations involved in multi-antenna wireless communications, one of those operations is complex matrix inversion. This thesis presents the verification and FPGA implementation of a SIMD processor, which was developed at Computer Engineering division of Linköping university, Sweden. This SIMD processor was designed specifically for performing complex matrix inversion in an efficient way, but it can also be reused for other operations. The processor is fully verified using all the possible combinations of instructions. An optimized firmware for this processor is implemented for efficiently inverting 4×4 matrices. Due to large number of subtractions involved in direct analytical approach, it losses stability for 4×4 matrices. Instead of this, a blockwise subdivision is used, in which 4×4 matrix is subdivided into four 2×2 matrices. Based on these 2×2 matrices, the inverse of 4×4 matrix is computed using the direct analytical approach and some other computations. Finally, the SIMD processor is integrated with Senior processor (a controlprocessor) and synthesized on Xilinx, Virtex-4 FPGA. After this, the performance of the proposed architecture is evaluated. A firmware is implemented for the Senior which uploads and downloads data/program into the SIMD unit using both I/O and DMA. / Den snabbt ökande prestandan hos digital elektronik har ökat behovet av Software Defined Radio (SDR), vilket inte var möjligt med tidigare hårdvara. Denna ökade förmåga kommer till priset av tidsåtgång, till följd av komplexa procedureri samband med trådlös kommunikation med flera antenner, en av dessa procedurer är komplex matrisinvertering. Denna avhandling presenterar verifiering och FPGA implementering hos en SIMD processor, vilken har blivit utvecklad vid institutionen för datorteknik, Linköpings universitet, Sverige. Denna SIMD processor blev specifikt designad för att genomföra komplex matrisinvertering på ett effektivt sätt, men kan också användas för andra tillämpningar. Processorn har testats och verifierats för alla möjliga kombinationer av instruktioner. En optimerad firmware för denna processor är implementerad för att effektivt invertera 4×4 matriser. På grund av att ett stort antal subtraktioner är inblandade i ett direkt analytiskt angreppssätt, så förlorar den stabilitet för 4×4 matriser. Istället används en stegvis indelning i underavdelningar, där 4×4 matrisen delasin i fyra 2×2 matriser. Baserat på dessa 2×2 matriser beräknas inversen av 4×4 matrisen med hjälp av ett direkt analytiskt angreppssätt samt andra beräkningar. Slutligen, SIMD processorn är integrerad i en huvudprocessor och körs påXilinx, Virtex-4 FPGA. Efter detta utvärderas prestandan hos den föreslagna arkitekturen. Firmware implementeras hos huvudprocessorn som laddar upp och ned data/program till SIMD enheten genom I/O samt DMA.

Rutiner skrivna i Verilog har utvecklats för avkodning av en frekvensmodulerad signal givet ett Analog Devices AD9874-chip. Olika metoder för I/Q-demodulation har utvärderats och av dessa har CORDIC valts och implementerats i Verilog. Koden har till viss del testats på en IGLOO nano-FPGA men framförallt simulerats och verifierats i ModelSim. / Routines written in Verilog have been developed to perform I/Q-demodulation of a frequency modulated signal given valuesfrom a Analog Devices AD9874 chip. Different methods for I/Q-demodulation have been evaluated and among theseCORDIC has been chosen and implemented in Verilog. The code has to some extent been tested on a IGLOO nano FPGA but foremost been simulated and verified in ModelSim.

This thesis is about creation of a Matlab program that suggests and automatically generates a Phase to Sine Amplitude Converter (PSAC) in the hardware language VHDL, suitable for Direct Digital Frequency Synthesis (DDFS). Main hardware target is Field Programmable Gate Arrays (FPGAs). Focus in this report is how an FPGA works, different methods for sine amplitude generation and their signal qualities vs the hardware resources they use. / Detta exjobb handlar om att skapa ett Matlab-program som föreslår och implementerar en sinusgenerator i hårdvaruspråket VHDL, avsedd för digital frekvenssyntes (DDFS). Ämnad hårdvara för implementeringen är en fältprogrammerbar grindmatris (FPGA). Fokus i denna rapport ligger på hur en FPGA är uppbyggd, olika metoder för sinusgenerering och vilka kvaliteter på sinusvågen de ger och vilka resurser i hårdvaran de använder.

This thesis focused on testing whether persistent encryption of Fibre Channel is doable and what kind of security it provides. It has been shown that intercepting, analysing and modifying Fibre Channel traffic is possible without any noticeable performance loss as long as latency is kept within certain boundaries. If latency are outside those boundaries extreme performance loss are to be expected. This latency demand puts further restrictions on the cryptography to be used. Two platforms were simulated, implemented and explained. One for intercepting and modifying Fibre Channel and one for analysing Fibre Channel traffic using Linux and Wireshark.

This is a master thesis in the field of information security. The problem area addressed is how to efficiency implement encryption and decryption of biometric image data in a FPGA. The objective for the project was to implement AES (Advanced Encryption Standard ) encryption in a Xilinx Kintex-7 FPGA with biometric image data as the application. The method used in this project is Design Science Research Methodology, in total three design and development iterations were performed to achieve the project objectives. The end result is a FPGA platform designed for information security research with biometric image as application. The FPGA developed in this project, is the first fully pipelined AES encryption/decryption system to run physically in a Kintex-7 device. The encryption core was made by Dr. Qiang Liu and his team while the fully pipelined decryption core was designed in this project. The AES encryption/ decryptions was further optimized to support image application by adding Cipher-block chaining to both the encryption and decryption. The performance achieved for the system was 40 GB/s throughput, 5.27 Mb/slice efficiency with a power performance of 286 GB/W. The FPGA platform developed in this project is not only limited to AES, other cryptography standards can be implemented on the platform as well. / <p>Validerat; 20140619 (global_studentproject_submitter)</p>

Submitted by Isaac Francisco de Souza Dias (isaac.souzadias@ufpe.br) on 2016-04-25T18:04:20Z No. of bitstreams: 2 license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) DISSERTAÇÃO Bruno Pessoa Neves.pdf: 2837976 bytes, checksum: adb9ef8e4e3ccc7abf1b6bac4c000360 (MD5) / Made available in DSpace on 2016-04-25T18:04:20Z (GMT). No. of bitstreams: 2 license_rdf: 1232 bytes, checksum: 66e71c371cc565284e70f40736c94386 (MD5) DISSERTAÇÃO Bruno Pessoa Neves.pdf: 2837976 bytes, checksum: adb9ef8e4e3ccc7abf1b6bac4c000360 (MD5) Previous issue date: 2015-08-19 / FACEPE / A computação de alto desempenho está presente em diversos setores do conhecimento humano. Ela busca atender a demanda por soluções para problemas em áreas como bioinformática, petroquímica, climatologia, dentre outros. Sabe-se que a grande maioria dessas áreas trabalha com quantidades massivas de dados, o que representa um desafio que a computação deve constantemente superar. Dentre algumas soluções atualmente adotadas, podemos citar os Field Programmable Gate Arrays (FPGAs). Esses dispositivos permitem explorar a computação paralela com menor consumo de energia quando comparados a Central Process Units (CPUs) e Graphic Process Units (GPUs). Além disso, os FPGAs permitem explorar o reuso de dados, o que possibilita o desenvolvimento de arquiteturas computacionais mais eficientes. Essas características fazem dos FPGAs uma opção atraente para se desenvolver soluções para problemas que possuem uma alta demanda por processamento, como em aplicações científicas. Essas aplicações normalmente fazem uso massivo de números em ponto flutuante. Em 1977 o Institute of Electrical and Electronics Engineers (IEEE) propõe a criação do padrão IEEE-754 para a implementação da aritmética de ponto flutuante em base binária. No entanto, o padrão só foi concluído e lançado mais tarde, em 1985. Esse padrão numérico permite ao mesmo tempo tanto uma grande precisão, quanto uma grande capacidade de representação. O padrão IEEE-754 passou a ser seguido pelos fabricantes de computadores e desenvolvedores de software no tratamento da aritmética binária computacional. A indústria petrolífera faz uso massivo da aritmética de ponto flutuante para o mapeamento e geração de imagem das camadas do subsolo para detecção de poços de hidrocarbonetos. Um dos métodos de imageamento sísmico que tem apresentando melhores resultados em áreas com litologias mais complexas, tais como no pré-sal, é o algoritmo Reverse Time Migration (RTM). Esse método faz uso de uma aproximação da equação de onda por meio dos operadores de diferenças finitas. Isso permite o mapeamento da variação dos campos de pressão e com isso se estimar as características litológicas das camadas em subsuperfície. Contudo, o custo do RTM é bastante elevado em termos computacionais. Por esse motivo, aplicações que otimizam desempenho ganham importância no cenário de mapeamento sísmico do subsolo realizado pelas indústrias petrolíferas. Esta dissertação aborda o desenvolvimento de um núcleo aritmético híbrido capaz de resolver a equação de diferenças finitas presentes no algoritmo de RTM, em FPGA. Foram desenvolvidos duas versões, uma totalmente em ponto flutuante padrão IEEE-754 e outra também com notação de ponto fixo para ganho de desempenho. / The high-performance computing is present in different sectors of human knowledge. It seeks to meet the demand for solutions to problems in areas such as bioinformatics, petrochemical, climatology, among others. It is known that the vast majority of these areas work with massive amounts of data, which is a challenge that the computational field should constantly overcome. Among some currently adopted solutions, we can mention the Field Programmable Gate Arrays (FPGAs). These devices allow exploit parallel computing with lower power consumption when compared to Central Process Units (CPUs) and Graphic Process Units (GPUs). Furthermore, FPGAs allow explore the data reuse, which enables the development of more efficient computing architectures. These characteristics make FPGAs an attractive option to develop solutions to problems that have a high demand for processing, such as in scientific applications. These applications typically make heavy use of floating point numbers. In 1977 the Institute of Electrical and Electronics Engineers (IEEE) proposes the creation of the IEEE-754 standard for implementing floating-point arithmetic in binary base. However, the standard was completed and released later in 1985. This numerical pattern allows the same time both a high precision, as a large capacity representation. The IEEE-754 standard then began to be followed by software developers and computer makers in the treatment of computer binary arithmetic. The oil industry makes massive use of floating-point arithmetic for mapping and generating image of the subsurface layers to detect hydrocarbon wells. One of seismic imaging methods that have presented better results in areas with more complex lithologies, such as the pre-salt, is the Reverse Time Migration algorithm (RTM). This method makes use of an approximation to the wave equation through the finite difference operator. This allows mapping the variation of pressure fields and thereby estimate the lithological characteristics of the layers in the subsurface. However, the cost of the RTM is computationally quite high. Therefore, applications that optimize performance gain importance in the underground seismic mapping scenario performed by the oil industry. This paper discusses the development of a hybrid arithmetic core able to solve the equation of finite differences present in the RTM algorithm in FPGA. Two versions, a fully floating point IEEE-754 standard and also with other fixed-point notation for performance gain were developed.