In this thesis, we present an FPGA implementation of parallel-node low-density-parity-check convolutional-code (PN-LDPC-CC) encoder and decoder. A 2.4 Gbit/s rate-1/2 (3, 6) PN-LDPC-CC encoder and decoder were implemented on an Altera development and education board (DE4). Detailed power measurements of the FPGA board for various configurations of the design have been conducted to characterize the power consumption of the decoder module. For an Eb/N0 of 5 dB, the decoder with 9 processor cores (pipelined decoder iteration stages) has a bit-error-rate performance of 10E-10 and achieves an energy-per-coded-bit of 1.683 nJ based on raw power measurement results. The increase in Eb/N0 can effectively reduce the decoder power and energy-per-coded-bit for configurations with 5 or more processor cores for Eb/N0 < 5 dB. The incremental decoder power cost and incremental energy-per-coded-bit also hold a linearly decreasing trend for each additional processor core. Additional experiments are performed to account for the effect of the efficiency of the DC/DC converter circuitry on the raw power measurement data. Further experiments have also been conducted to quantify the effect of clipping thresholds, bit width for each processor core on bit-error-rate (BER) performance, power consumption, and logic utilization of the decoder. A “6Core" decoder with growing bit-width log-likelihood ratios (LLRs) has been found to have a BER performance near that of a “6Core" 6-bit decoder while consuming similar power, and logic utilization to that of a 5-bit “6Core" decoder.

In the past two decades, FPGA has been witnessed from its restricted use as glue logic towards real System-on-Chip (SoC) platforms. Profiting from the great development on semiconductor and IC technologies, the programmability of FPGAs enables themselves wide adoption in all kinds of aspects of embedded designs. Modern FPGAs provide the additional capability of being dynamically and partially reconfigured during the system run-time. The run-time reconfigurability enhances FPGA designs from the sole spatial to both spatial and temporal parallelism, providing more design flexibility for advanced system features. Adaptive computing delegates an advanced computing paradigm in which computation tasks and resources are intelligently managed in correspondence with conditional requirements. In this thesis, we investigate adaptive designs on FPGA platforms: We present a comprehensive and practical design framework for adaptive computing based on the FPGA run-time reconfigurability. It concerns several design key issues in different hardware/software layers, specifically hardware architecture, run-time reconfiguration technical support, OS and device drivers, hardware process scheduler, context switching as well as Inter-Process Communications (IPC). Targeting a special application of data acquisition (DAQ) and trigger systems in nuclear and particle physics experiments, we set up the data streaming model and conduct theoretical analysis on the adaptive system. Three application studies are employed to verify the proposed adaptive design framework: The first application demonstrates a peripheral controller adaptable system aiming at general embedded designs. Through dynamically loading/unloading a NOR flash memory controller and an SRAM controller, both flash memory and SRAM accesses may be accomplished with less resource consumption than in traditional static designs. In the second case, two real algorithm processing engines are adaptively time-multiplexed in the same reconfigurable slot for particle recognition computation. Experimental results reveal the reduced on-chip resource requirements, as well as an approximate processing capability of the peer static design. Taking advantage of the FPGA dynamic reconfigurability, we present in the third application a novel on-FPGA interconnection microarchitecture named RouterLess NoC (RL-NoC). RL-NoC employs the novel design concept of Move Logic Not Data (MLND), and significantly distinguishes itself from the existing interconnection architectures such as buses, crossbars or NoCs. It does not rely on routers to deliver packets hop by hop as canonical NoCs do, but buffers data packets in virtual channels and brings various nodes using run-time reconfiguration to produce or consume them. In comparison with canonical packet-switching NoCs, the routerless architecture features lower design complexity, less resource consumption, higher work frequency, more efficient power dissipation as well as comparable or even higher packet delivery efficiency. It is regarded as a promising interconnection approach in some design scenarios on FPGAs, especially for light-weight applications. / QC 20110531

Modern high-performance digital signal processing (DSP) applications face constantly increasing performance requirements and are becoming increasingly challenging to develop and work with. In DSP paradigm, many researchers see potential in achieving algorithm speed-up by employing Field Programmable Gate Arrays (FPGAs) – reconfigurable hardware with parallelism feature. However, developing applications for FPGAs incur particular challenges on the development flow. This work proposes a scalable hybrid DSP system for performing high-performance signal processing applications. The system employs hybrid CPU + FPGA architecture of commercially available, off-the-shelf (COTS) FPGAs and central processing units (CPU) of personal computers. In this work an example implementation of a multi-channel cross-correlator is investigated and delivered using a new development paradigm. The correlator is implemented on the XD1000 development system using a high-level FPGA programming tool – Impulse CoDeveloper. Analysis of DSP application development in a hybrid CPU+FPGA system employing the high-level programming tool Impulse C is presented. Potential of the selected tool to deliver algorithm speed-ups is investigated using reference multi-channel correlator software. Particular attention is devoted to input/output (I/O) implementation, which is considered one of the most challenging problems in FPGA design development. This work delivers an I/O framework based on PCI Express interface for the proposed high-performance scalable DSP system. Using Stratix II GX PCI Express Development Board from Altera Corporation, a scalable and flexible communication approach for the multi-channel correlator is delivered. This framework can be adapted to perform other high-performance streaming DSP applications. The outcomes of this work are a multi-channel correlator developed in a reconfigurable environment with new design methodology and I/O framework with software control application. The outcomes are used to demonstrate the potential of implementing DSP applications in hybrid CPU + FPGA architecture and to discuss existing challenges and suggest possible solutions.

This project investigates a self-reconfiguring rSoC (reconfigurable System on Chip) system which automatically and dynamically loads peripheral controllers, based on the peripherals connected to the system. The Xilinx Virtex-II FGPA, which supports dynamic partial reconfiguration, is used as the experimental target. To implement the system, three main areas are investigated: the peripheral auto detection, the dynamic partial reconfiguration mechanism on the FPGA, and the supporting software. The system core is designed as two defined areas on a single FPGA chip. A fixed area is used for the constant logic circuits (such as soft-core CPU) and partial reconfiguration (PR) slots are used for changeable peripheral controllers. The autoconfiguration process involves three different steps: peripheral auto detection, loading of a peripheral hardware interface configuration, and loading of a peripheral software driver. In our system, we successfully implement the mechanism of peripheral dynamic loading on the rSoC system. Four novel features are provided in the system: 1) Peripheral auto detection. Peripheral boards are automatically detected by the system when connected to the system. 2) Peripheral controller hardware bitstream and software driver dynamic loading. The required peripheral controller hardware bitstream for the connected peripheral board is automatically searched for and loaded by the operating system, as well as the required software driver. Manual operations on these processes are also supported. 3) Individual interface to external environment. Each PR slot provides individual interface to peripheral boards. It is configured by each peripheral controller for board-specific connection. 4) The existing system is extensible. The partial reconfiguration mechanism provided in this project supports at least two PR slots. On higher capacity FPGAs, the number of PR slots could be increased. In our existing system, the time used for the dynamic partial reconfiguration process, including the hardware bitstream loading and the software driver loading, is in the order of 10-20ms, which is an insignificant fraction of the Linux boot time.

Σκοπός της διπλωματικής εργασίας αυτής είναι μεσω του σχεδιασμού και της υλοποίησης της συνάρτησης κατακερματισμού Skein να κατανοηθούν σε βάθος οι αρχές της σχεδίασης κυκλωμάτων μεγάλης κλίμακας σε διαφορετικές πλατφόρμες υλικού. Στην ερχασία αυτή σχεδιάζονται και εξομοιώνονται η λειτουργία τεσσάρων κυκλωμάτων - υλοποιήσεων της συνάρτησης με διαφορετική σκόπευση η καθεμία και συγκρίνονται μεταξύ τους με βάση καλά ορισμένα κριτήρια και εξάγονται χρήσιμα συμπεράσματα. / -

Η παρούσα διπλωματική εργασία πραγματεύεται σχεδιασμούς και υλοποιήσεις σε υλικό αρχιτεκτονικών για κρυπτογραφικές συναρτήσεις κατακερματισμού. Στόχος ήταν η ανάπτυξη αρχιτεκτονικών πολλαπλών λειτουργιών για συναρτήσεις κατακερματισμού της οικογένειας Secure Hash Algorithms (SHA). Αναλυτικότερα, αρχικά έλαβε χώρα μελέτη τριών συναρτήσεων κατακερματισμού, και συγκεκριμένα των SHA-1, SHA-256 και SHA-512, καθώς και των αντίστοιχων αρχιτεκτονικών τους (τέσσερα στάδια pipeline). Στη μελέτη αυτή έγινε ανάλυση και εντοπισμός ομοιοτήτων και διαφορών των αρχιτεκτονικών αυτών, όσον αφορά τα δομικά τους στοιχεία και τις επιμέρους παραμέτρους τους. Με βάση τα αποτελέσματα αυτά, και αξιοποιώντας τις ομοιότητες των αρχικών αρχιτεκτονικών, σχεδιάστηκαν δύο αρχιτεκτονικές πολλαπλών λειτουργιών με τέσσερα στάδια pipeline: α) η SHA-1/256 που ενσωματώνει τις λειτουργίες των SHA-1 και SHA-256 αλγορίθμων και b) η SHA-1/256/512 που ενσωματώνει τις λειτουργίες και των τριών. Λόγω της παραπάνω αξιοποίησης, οι αρχιτεκτονικές αυτές παρουσιάζουν μικρή απώλεια σε ταχύτητα, ενώ ταυτόχρονα η επιφάνεια ολοκλήρωσης κρατείται σε χαμηλά επίπεδα. Η ορθή λειτουργία των παραπάνω αρχιτεκτονικών επιβεβαιώθηκε, αρχικά, μέσω εξομοίωσης με το ModelSim της Mentor Graphics, Στη συνέχεια, εκτελέστηκε σύνθεση και place-&-route των αρχιτεκτονικών σε FPGAs της Xilinx (οικογένειες Virtex-4, Virtex-5, Virtex-6) με χρήση της σουίτας Xilinx ISE Design Suite v12.1, από όπου προέκυψαν οι μετρικές της απόδοσής τους (συχνότητα, επιφάνεια, ρυθμαδόποση). Τέλος, πραγματοποιήθηκε, ενδεικτικά, υλοποίηση της αρχιτεκτονικής SHA-1/256 στο board Spartan 3E (xc3s500E) και εκ νέου επιβεβαίωση της ορθής λειτουργίας. / This thesis deals with the design and implementation in hardware architectures for cryptographic hash functions. The aim was to develop multi-mode architectures for the Secure Hash Algorithms (SHA) famylies. Specifically, the study initially held three hash functions, namely SHA-1, SHA-256 and SHA-512, as well as their respective architectures (four-stage pipeline). This study has analyzed and identified similarities and differences of these architectures, on their components and sub-parameters. Based on these results, and using the similarities of the original architecture, we designed two multi-mode architectures with four-stage pipeline: a) SHA-1/256 that integrates the functions of the SHA-1 and SHA-256 algorithms and b) the SHA -1/256/512 incorporating the functions of all three. Due to the above use, the architectures have little loss in speed, while the chip area is kept low. The proper functioning of these architectures was, initially, through simulation with ModelSim (Mentor Graphics), then performed synthesis and place-&-route architectures of FPGAs to Xilinx (families of Virtex-4, Virtex-5, Virtex-6) using the Xilinx ISE Design Suite v12.1, from which emerged the metrics of performance (frequency, area, throughput). Finally, for demonstration reasons, an implementation of the architecture SHA-1/256 board Spartan 3E (xc3s500E) and re-confirmation of its correct operation took place.

The cable television (CATV) industry has grown significantly since its inception in the late 1940’s. Originally, a CATV network was comprised of several homes that were connected to community antennae via a network of coaxial cables. The only signal processing done was by an analogue amplifier, and transmission only occurred in one direction (i.e. from the antennae/head-end to the subscribers). However, as CATV grew in popularity, demand for services such as pay-per-view television increased, which lead to supporting transmission in the upstream direction (i.e. from subscriber to the head-end). This greatly increased the signal processing to include frequency diplexers. CATV service providers began to expand the bandwidth of their networks in the late 90’s by switching from analogue to digital technology. In an effort to regulate the manufacturing of new digital equipment and ensure interoperability of products from different manufacturers, several cable service providers formed a non-for-profit consortium to develop a data-over-cable service interface specification (DOCSIS). The consortium, which is named CableLabs, released the first DOCSIS standard in 1997. The DOCSIS standard has been upgraded over the years to keep up with increased consumer demand for large bandwidths and faster transmission speeds, particularly in the upstream direction. The latest version of the DOCSIS standard, DOCSIS 3.1, utilizes orthogonal frequency-division multiple access (OFDMA) technology to provide upstream transmission speeds of up to 1 Gbps. As cable service providers begin the process of upgrading their upstream receivers to comply with the new DOCSIS 3.1 standard, they require a means of testing the various functions that an upstream receiver may employ. It is convenient for service providers to employ cable modem (CM) plus channel emulator to perform these tests in-house during the product development stage. Constructing the emulator in digital technology is an attractive option for testing. This thesis approaches digital emulation by developing a digital model of the CMs and upstream channel in a DOCSIS 3.1 network. The first step in building the emulator is to simulate its operations in MATLAB, specifically upstream transmission over the network. The MATLAB model is capable of simulating transmission from multiple CMs, each of which transmits using a specific “transmission mode.” The three transmission modes described in the DOCSIS 3.1 standard are included in the model. These modes are “traffic mode,” which is used during regular data transmission; “fine ranging mode,” which is used to perform fine timing and power offset corrections; and “probing” mode, which is presumably used for estimating the frequency response of the channel, but also is used to further correct the timing and power offsets. The MATLAB model is also capable of simulating the channel impairments a signal may encounter when traversing the upstream channel. Impairments that are specific to individual CMs include integer and fractional timing offsets, micro-reflections, carrier phase offset (CPO), fractional carrier frequency offset (CFO), and network gain/attenuation. Impairments common to all CMs include carrier hum modulation, AM/FM ingress noise, and additive white Gaussian noise (AWGN). It is the hope that the MATLAB scripts that make up the simulation be translated to Verilog HDL to implement the emulator on a field-programmable gate array (FPGA) in the near future. In the event that an FPGA implementation is pursued, research was conducted into designing efficient fractional delay filters (FDFs), which are essential in the simulation of micro-reflections. After performing an FPGA implementation cost analysis between various FDF designs, it was determined that a Kaiser-windowed sinc function FDF with roll-off parameter β = 3.88 was the most cost-efficient choice, requiring at total of 24 multipliers when implemented using an optimized structure.

Made available in DSpace on 2013-08-07T18:43:13Z (GMT). No. of bitstreams: 1 000417206-Texto+Completo-0.pdf: 2684469 bytes, checksum: eee55b180d3981f3bad747667dc61538 (MD5) Previous issue date: 2009 / The evolution of the integrated circuit manufacturing technology is still following the so called Moore Law. However, scientific applications growingly require high performance computational resources, motivating researchers to propose the acceleration of such applications through the use of dedicated hardware devices. Often, due to the need of obtaining fast results in the design of these applications the use of reconfigurable hardware devices is recommended. Currently, there is a significant increase in the amount of research on molecular biophysics with a main goal on the design of drugs. Nonetheless, to achieve the design of a new drug and the possible cure of some disease, several complex procedures must be undertaken. As examples, it is possible to cite experiments to determine the behavior of simple molecules or proteins. Molecular dynamics simulations can reveal a large variety of facts about the molecular system under scrutiny. But to execute such simulations in a timely way, it is necessary to employ a huge amount of high performance computational resources, like supercomputers, large computer clusters or grids. This is due to the enormous amount of mathematical computations to perform, to the amount of generated information and to the need to obtain all this information in short time delays. This makes the requirement for high performance computing a basic characteristic of this field. To fulfill the computational requirements of molecular dynamics simulations there are FPGA based platforms, which are frequently employed as hardware accelerators for applications with high computational cost. FPGAs are widely available and enable the fast design and implementation of dedicated hardware with high performance when compared to software running on general purpose processors. The main contribution of this work is the proposition of a communication method between a host computer and a reconfigurable hardware platform based on FPGAs. The dissertation suggests a software architecture for integrating software and hardware platforms used to accelerate molecular dynamics simulation applications. The proposition has been implemented as an Application Programming Interface (API) that organizes the communication between platforms in several service abstraction levels, with the goal of rendering the application software layers independents of the accelerator hardware. / A evolução da tecnologia de fabricação de circuitos integrados continua obedecendo à lei de Moore. Entretanto, aplicações científicas cada vez mais necessitam de recursos de alto desempenho computacional, motivando pesquisadores a propor a aceleração por hardware dedicado para aumentar o desempenho destas aplicações. Freqüentemente, devido à necessidade de rapidez no projeto de tais aplicações, empregam-se técnicas de projeto com emprego de hardware reconfigurável. Atualmente, há um grande aumento em pesquisas de biofísica molecular com o objetivo principal na concepção de fármacos. Porém, para se chegar até a droga e a possível cura de alguma doença, diversos procedimentos devem ser empreendidos. Como exemplos podem ser citados experimentos para determinar o comportamento de moléculas simples ou de proteínas. As simulações por dinâmica molecular aportam uma variedade de informações do sistema molecular em questão. Entretanto, para se executar estas simulações é necessário o auxílio de recursos computacionais de alto desempenho, devido à elevada quantidade de cálculos a efetuar, à quantidade de informações geradas e à necessidade destas informações e resultados em períodos curtos de tempo, tornando a exigência por computação de alto desempenho uma característica básica desta área. Para suprir a exigência computacional de simulações por dinâmica molecular existem plataformas baseadas em FPGAs, que são largamente utilizadas como aceleradores de hardware de aplicações com alto custo computacional. FPGAs são amplamente disponíveis e permitem realizar rapidamente o projeto e a implementação de hardware com alto desempenho se comparado a software executando em processadores de propósito geral.A principal contribuição deste trabalho é uma proposta de método de comunicação entre uma máquina hospedeira e uma plataforma de hardware reconfigurável baseada em FPGAs, sugerindo uma arquitetura de software para integração das plataformas de software e o hardware usado para acelerar aplicações de simulação por dinâmica molecular. A proposta foi implementada como uma API para organização da comunicação entre as plataformas em níveis de abstração de serviço, visando tornar as camadas de software independentes do hardware.

Made available in DSpace on 2013-08-07T18:43:13Z (GMT). No. of bitstreams: 1 000421786-Texto+Completo-0.pdf: 6104492 bytes, checksum: 1d8dad6aa25fe5104f08a43d444e3017 (MD5) Previous issue date: 2009 / The current state of electronic circuit design and fabrication processes enables the integration of more than a billion devices in a single integrated circuit. A state of the art integrated circuit is a complex component formed by several complex modules known as intellectual property cores. Modern integrated circuits contain dozens or hundreds of such cores interconnected. The interconnection of cores is growingly performed through complex communication structures. One way to organize such interconnect architectures is to build them in the form of an intrachip network. The use of totally or partially regular communication structures improves scalability and the degree of communication parallelism in complex integrated circuits. One of the most important characteristic of intrachip networks is its topology. This work approaches the verification and prototyping of the Hermes-TB intrachip network. This network employs a regular, bidirectional 2D torus topology as a means to reach low latency and high throughput communication at a reasonable hardware cost. The Hermes-TB design verification was achieved through the use of timing simulation of the original design, since the original proposal of the network employed only functional simulation as design validation method. Prototyping of Hermes-TB, on the other hand, was conducted on an FPGA-based platform, and served to validate the network design in hardware for the first time. At the end of this work, it was then possible to confirm the viability to use the Hermes-TB intrachip network in real circuits. / O avanço tecnológico atual do processo de construção de circuitos eletrônicos possibilita a integração de mais de um bilhão de componentes em um único circuito integrado. Um circuito integrado no estado da arte é um componente complexo constituído por numerosos módulos complexos conhecidos como núcleos de propriedade intelectual. Circuitos integrados modernos contêm dezenas ou centenas de núcleos interconectados. Cada vez mais a interconexão de núcleos se faz através de estruturas de comunicação complexas. Uma forma de organizar estas arquiteturas é construí-las sob a forma de uma rede intrachip. O uso de estruturas de comunicação total ou parcialmente regulares tende a aumentar a escalabilidade e o grau de paralelismo da comunicação em sistemas integrados complexos. Uma das características mais importantes de uma rede intrachip é a sua topologia. Este trabalho aborda a verificação e a prototipação da rede intrachip Hermes-TB. Esta rede emprega topologia do tipo toro 2D bidirecional como forma de alcançar baixa latência e alta vazão a um custo de hardware reduzido. A verificação do projeto da Hermes-TB foi obtida aqui através da execução da simulação com atrasos do projeto original, pois a proposta inicial da rede realizou a validação do projeto apenas através de simulação funcional. Por outro lado a prototipação, aqui realizada sobre plataformas baseadas em FPGAs (do inglês, Field Programmable Gate Arrays) validou o projeto pela primeira vez em hardware. Ao final deste trabalho pôde-se então confirmar a viabilidade de uso da rede intrachip Hermes-TB em circuitos reais.

This thesis describes the design of the data datalogger for collecting the operating data of the machine tool. Dataloggers and data acquisition systems are used in scientific research as well as in the industry for recording and analyzing large amounts of data. The control unit of the proposed system is the National Instruments CompactRIO platform. System software is created in the LabVIEW programming environment and uses both the FPGA circuit and the real-time processor of the control unit. Measured data are stored on the unit and in the database. The measurement status is reported via email.