<p>This Master's Thesis describes the design of a new system where a digital signal processor has been added to an existing imaging system consisting of field programmable gate arrays. The new system will offer a higher degree of flexibility by considerably shortening the design time and make it possible to implement more complex algorithms than the existing ones. </p><p>The choice of system architecture and a test implementation are discussed. The test implementation consists of a program for the digital signal processor and VHDL code for one of the field programmable gate arrays. </p><p>The code for the digital signal processor was designed for testing on an evaluation board from Texas Instruments. The evaluation board is connected to a computer, which runs a Windows program to visualize the result. </p><p>The choice of algorithm has not been made yet. In the test implementation a skewing algorithm is used as an example. Two implementations of the skewing algorithm has been optimized, one fix point version and one floating point version.</p>

<p>The target of this master thesis is to evaluate the Image Warping technique and propose a possible design for an implementation in FPGA. The Image Warping is widely used in the image processing for image correction and rectification. A DSP is a usual choice for implantation of the image processing algorithms, but to decrease a cost of the target system it was proposed to use an FPGA for implementation.</p><p>In this work a different Image Warping methods was evaluated in terms of performance, produced image quality, complexity and design size. Also, considering that it is not only Image Warping algorithm which will be implemented on the target system, it was important to estimate a possible memory bandwidth used by the proposed design. The evaluation was done by implemented a C-model of the proposed design with a finite datapath to simulate hardware implementation as close as possible.</p>

<p>Detta dokument beskriver hur man kan använda kameramodulen TRDB DC2 från Terasic tillsammans med ett utvecklingskort DE2 för Alteras FPGA-kretsar. Kamerabilder överförs från kameramodulen till en VGA-skärm. VGA-bilden har en upplösning på 640 x 480 pixlar och 10bitars upplösning på färgerna. Systemet presterar maximalt 15 bilder per sekund och det är själva bildsensorn som sätter den begränsningen, man kan bla ändra exponeringstid och frysa bilden om man så vill. Hela projektet är skrivet i VHDL och arbetet är gjort i Quartus 6.0 från Altera. VHDL-koden är skriven i första hand för att vara lättförståelig och enkel att modifiera, några större ansträngningar för att minimera hårdvara eller på annat sätt effektivisera konstruktionen har inte gjorts.</p>

<p>This diploma work describes how an FPGA is designed to control a CAN controller. It describes the different tools used when working with Actel’s design tools and the sequence of work applied. It gives a short overview of a multiplexer, the CAN bus, an analog/digital-converter and some more information on the actual FPGA. It also brings up the design process of the FPGA, planning, coding, simulating, testing and finally programming the FPGA. The different parts implemented in the FPGA are a shift-register and two state- machines that are connected with each other. They work together to control the SJA1000 CAN controller made by Philips. They also receive data from the analog/digital-converter that they forward onwards to the CAN controller that forward the data on the CAN bus.</p>

<p> </p><p>Examensarbetsuppgiften har gått ut på att genomföra en prestandajämförelse mellan en hård och en mjuk processorkärna integrerad i en FPGA, i detta fall, en Virtex4 FX12 från Xilinx.</p><p>System med de olika kärnorna har tagits fram, där antalet klockcykler för att genomföra olika beräkningar har mäts. Bland annat har algoritmen Fast Fourier Transform och dess invers beräknats för en vektor.</p><p>De kärnor som har provats är den mjuka MicroBlaze framtagen av Xilinx samt den hårda PowerPC 405. Prestandan för systemet med mjuk kärna var 65 % av det med hård kärna</p><p>Förutom prestandamätningarna har en vidare teoretisk jämförelse mellan kärnorna genomförts. Utifrån den har slutsatsen dragits att när man behöver små volymer av FPGA-kretsar eller flera olika beräkningar skall göras är FPGAer med hård kärna att föredra. Om det är större volymer eller bara ett fåtal typer av beräkningar som skall utföras är en mjuk kärna mest fördelaktig, främst av ekonomiska skäl. Likaså om krav finns på att processorarkitekturen är anpassad efter specifika önskemål.</p> / <p>The purpose of the master thesis has been implementation of a performance comparison between hard and soft CPU cores integrated in FPGA, in this case, a <em>Virtex4 FX12</em> from Xilinx.</p><p>Test designs for the various kernels have been developed, where the amount of clock cycles to carry out a set of calculations have been measured. In particular, the algorithm Fast Fourier Transform and its inverse have been studied.</p><p>The cores that have been tested are the soft MicroBlaze developed by Xilinx, and the hard PowerPC 405. The results state that the performance of the soft kernel was 65% of the hard one.</p><p>In addition to performance tests, a further theoretical comparison of the two kernels has been made. On the basis of the above it has been concluded that when small quantities of FPGA-circuits are needed or several different calculations have to be done, a hard core is preferable. If there are larger volumes needed or just a few types of calculations to be made, a soft core is advantageous, primarily for economic reasons, as is the case if there is requirement of a processor core tailored for specific needs.</p>

The goal of this research was to explore a new and improved software development tool for the implementation of control algorithms on Xilinx Field Programmable Gate Arrays (FPGA). The Simulink plug in, System Generator, complements traditional Hardware Description Language (HDL) by providing a higher level graphical language for the development of FPGA designs. The design is then translated into the lower level required by the Xilinx's ISE program. By utilizing this graphical based higher level of abstraction at the design entry level, the requirement of a detailed knowledge of HDL languages is no longer required. Because of this new environment the time required to implement the previously developed control design on the FPGA is reduced. The initial work began with a study of System Generator capabilities. One of the primary areas of interest is the difference on how the mathematical model representations are implemented between Simulink and the logic based hardware. From this initial work, a methodology for conversion between the developed and verified Simulink design and hardware implementation was obtained. As a case study, a control design was implemented for a Simulink model of an Unmanned Ground Vehicle (UGV) based on an RC-Truck. The control system consists of a simple mission planner to generate a vector of waypoints, a proportional-integral velocity controller and a proportional heading controller. The derived hardware design process is then utilized and validated by converting the control system into the available System Generator blocks. The final verification of the FPGA design was a hardware-in-the-loop simulation utilizing a Xilinx prototyping board. This design example demonstrated the validity of the presented approach as an efficient and reliable method for rapid system prototyping for designs developed within the Simulink environment.

A new instrument for conducting astronomical searches for nanosecond-scale optical pulses has been designed, built, and is now operating at Oak Ridge Observatory in Harvard, MA. The Advanced All-sky Camera, based on the previous generation ASIC-based design, is implemented using Xilinx Virtex-5 LX110 FPGAs to create a flexible and configurable system. Each FPGA has 32 1.5 Gsps analog-to-digital converters, implemented as 8-level flash ADCs using 256 of the Virtex-5's LVDS input pairs. Thirty-two FPGAs in the system total 1024 ADC channels, each with 8kB of sample memory, for triggering on and recording coincident pulse waveforms from an array of 1024 photomultiplier tube anodes. / Engineering and Applied Sciences

In this work we review the problem of radar imaging satellites' dependency on ground stations to transfer the image data. Since synthetic aperture radar images are very big, only ground stations are equipped to transfer that much data. This is a problem for maritime surveillance as it creates delay between the imaging and processing. We propose a new hardware algorithm that can be used by a satellite to detect ships and extract information about them, and since this information is smaller it can be relayed to reduce the delay significantly. For ship detection, an adaptive thresholding algorithm with exponential model is used. This algorithm was selected as it is the best fit for single-look radar images. For the property calculation, a data accumulating, single-look, connected component labeling algorithm is proposed. This algorithm accumulates data about the connected components, which is then used to calculate the properties of ships using image moments. The combined algorithm was then validated on Radarsat-2 images using Matlab for software and co-simulation for hardware. / Graduate

MP3, or MPEG-1 Layer 3, is the most widely-used format for storing compressed audio. MP3 is more advantageous than uncompressed audio (PCM), offering a much smaller size but without a noticeable loss in audio quality. This report will demonstrate decoding and playback of MP3 audio using a TLL5000 FPGA board. / text

Σε αυτήν την διπλωματική εργασία, υλοποιήθηκε ο κρυπτογραφικός αλγόριθμος Keccak σε σύστημα FPGA. Σχεδιάστηκαν τρεις αρχιτεκτονικές υλοποίησης, η κάθε μία με σκοπό την υλοποίηση ενός στόχου. Η πρώτη είχε σκοπό την απλή υλοποίηση του αλγορίθμου, η δεύτερη την αύξηση της ρυθμαπόδοσης και η τρίτη την μείωση του υλικού που χρησιμοποιείται. Στο τέλος, υπάρχει μια σύγκριση των σχεδιάσεων μεταξύ τους, αλλά και με κάποιες άλλες που έχουν δημοσιευτεί τα τελευταία χρόνια. / In this thesis, cryptographic algorithm Keccak was implemented for FPGA systems. There were three designs proposed, each one with a different goal to accomplish. The first one was a simple implementation, the second one aimed at increasing throughput and the third one aimed at reducing the amount of area used. At the end, there is a comparison between those designs and, also, some of those published in recent years.