The task is to build an intelligent sensor that can instruct a Lego robot to perform certain tasks. The sensor is mounted on the Lego robot and it contains a digital camera which takes continuous images of the front view of the robot. These images are received by an FPGA which simultaneously saves them in an external storage device (SDRAM). At one time only one image is saved and during the time it is being saved, FPGA processes the image to extract some meaningful information. In front of digital camera there are different objects. The sensor is made to classify various objects on the basis of their color. For the classification, the requirement is to implement color image segmentation based object tracking algorithm on a small Field Programmable Gate array (FPGA). For the color segmentation in the images, we are using RGB values of the pixels and with the comparison of their relative values we get the binary image which is processed to determine the shape of the object. A histogram is used to retrieve object‟s features and saves results inside the memory of FPGA which can be read by an external microcontroller with the help of serial port (RS-232).

The remotely operated underwater vehicles that the client develops have needs of different kinds of data channels. In order to minimize the need of physical cable between the control unit and a ROV, a multiplex protocol has been developed. The protocol has been designed with the aim of using the bandwidth of the transferring link as efficient as possible. The different kinds of data channels used during this thesis project is; RS232, RS485 and CAN. ROM and FIFO-memories have been used to be able to effectively manage the different data channels. All the reading and sending of these channels have been implemented in FPGA-technology, the coding is made generic so that it will be easier to add more channels to the system in the future. The multiplex protocol is a modified version of the method STDM and it is a proprietary protocol. Calculations has been made in MatLab to ensure that the protocol does not exceed the maximal bandwidth that is available. The protocol utilizes the error-detecting technique CRC for the purpose of error detection. A PCB has been developed during this thesis project, the PCB is made so that the different data channels have connection with the FPGA circuit.

This thesis is focused on developing a robust algorithm for recognition of road signs including all stages of a machine vision system i.e. image acquisition, pre-processing, colour segmentation, labelling and classifi-cation. Images are acquired by two different imaging systems and noise removal is done by applying Mean filter. Furthermore, different colour segmentation methods are investigated to find out the most high-performance approach and after applying dynamic segmentation based on blue channel in YCbCr colour space, the obtained binary image is transferred to a personal computer through the developed PC software using standard serial port and further processing and classification is run on the PC. Histogram of Oriented Gradients (HOG) is used as the main feature for recognition of road signs and finally the classification task is fulfilled by employing hardware efficient Minimum Distance Classifier (MDC).

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This diploma work describes how an FPGA is designed to control a CAN controller. It describes the different tools used when working with Actel’s design tools and the sequence of work applied. It gives a short overview of a multiplexer, the CAN bus, an analog/digital-converter and some more information on the actual FPGA. It also brings up the design process of the FPGA, planning, coding, simulating, testing and finally programming the FPGA. The different parts implemented in the FPGA are a shift-register and two state- machines that are connected with each other. They work together to control the SJA1000 CAN controller made by Philips. They also receive data from the analog/digital-converter that they forward onwards to the CAN controller that forward the data on the CAN bus.

Att ett grafikkort ska behandla data och sen generera en bild på en skärm är en ganska logisk funktion för ett grafikkort. Vad som har gjorts här är att alla grundläggande funktioner för grafikkortet har tagits bort, detta för att ingen behandling ska göras. Detta har gjorts för att kunna låta data passera genom kortet med så hög hastighet som möjligt. Att låta data gå genom kortet var det första steget. Efter det skulle förhoppningsvis ett stabilt system ha uppnåtts där vi kunde göra överföringen av data snabbare. Tyvärr blev det inte tillräckligt stabilt och vår slutsats är att man inte kan använda detta kort på det här sättet. För att kunna genomföra detta programmerades FPGA:n med VHDL-kodning. Innan VHDL programmeringen så studerades manualen för kortet för att veta hur de olika registrena på kortet skulle ställas in. För att testa programmering konstruerades en räknare som genererade en trekantsvåg på ett inkopplat oscilloskop. Den ursprungliga uppgiften klarades av. Detta var att skicka igenom data utan den skulle behandlas.

Heat, clock scew and frequency optimization are some of the problems a semiconductor designer must face. By splitting a synchrounous block into multiple pieces which comunicates asynchronously with eachother and provide them with independent clocks, these problems may be reduced. GALS (Global Asynchronous Local Synchronous) is a wrapper that wraps a synchronous block and provides it with a clock. Multiple GALS-elements will make the whole system. The clockfrequency may be independently adjusted between each block. The clocks may be started and halted independantly depending on the workload. Describing the system in a hardware language as VHDL, and implement it into an FPGA (Field Programmable Grid Array), makes the development of applications fast and cheap.

A design methodology to mitigate timing problems due to long wire delays is proposed. The timing problems are taking care of at architecture level instead of layout level in this design method so that no change is needed when the whole design goes to backend design. Hence design iterations are avoided by using this design methodology. The proposed design method is based on STARI architecture, and a novel initialization mechanism is proposed in this paper. Low frequency global clock is used to synchronize the communication and PLLs are used to provide high frequency working clocks. The feasibility of new design methodology is proved on FPGA test board and the implementation details are also described in this paper. Only standard library cells are used in this design method and no change is made to the traditional design flow. The new design methodology is expected to reduce the timing closure effort in high frequency and complex digital design in deep submicron technologies.

This report documents the work done by the author to design and implement a 3D graphics system on an FPGA (Field Programmable Gate Array). After a preamble with a background presentation to the project, a very brief introduction in computer graphics techniques and computer graphics theory is given. Then, the hardware available to the project, along with an analysis of general requirements is examined. The following chapter contains the proposed graphics system design for FPGA implementation. A broad approach to separate the design and the eventual implementation was used. Two 3D pipelines are suggested - one fully capable high-end version and one which use minimal resources. The documentation of the effort to implement the minimal graphics system previously discussed then follows. The documentation outlines the work done without going too deep into detail, and is followed by the largest of the tests conducted. Finally, chapter seven concludes the project with the most important project conclusions and some suggestions for future work.

This Bachelor thesis is a pre-study of the possibilities of using programmable logic in the purpose to enable fast trigger based data communication. Triggerbased data communication is in this case referred to a context where the processed data is stored and examined so when the trig situation appears the data should be able read out to a computer for evaluating. The purpose of this thesis is to find difficult and time consuming elements but also to find elements that is well suited for implementation in programmable logic. The work should also support further development and verification of trig functionalities and additional hardware. This with the intent of constructing an Ethernet based oscilloscope. The result of this thesis is a conclusion that programmable logic is well suited for many of the implemented logic function