FPGA-CF is an open-source, portable, extensible communications framework that consists of a small hardware core (less than 600 slices) and a software library/API (Java and C++). It enables a host PC to transmit data at 120 Mb/s to Xilinx-based FPGA boards via Ethernet using standard inter-networking protocols (UDP/IP). A custom lightweight connection-oriented protocol guarantees reliability. The hardware core is directly connected to the Xilinx internal configuration port (ICAP) and supports all ICAP functionality. The core also provides an extensible user-channel interface and provides up to 15, 8-bit user-data channels that can be connected to user circuitry (configurable by the user). The host software API supports both Java and C++ and provides high-level functionality for making connections and transmitting data. The utility of the system is demonstrated by implementing an on-chip test/debug system using FPGA-CF.

With the growing density and shrinking feature size of modern semiconductors, it is increasingly difficult to manufacture defect free semiconductors that maintain acceptable levels of reliability for long periods of time. These systems are increasingly susceptible to wear-out by failing to meet their operational specifications for an extended period of time. The reconfigurability of FPGAs can be used to repair post-manufacturing faults by configuring the FPGA to avoid a damaged resource. This thesis presents a method for preemptively preparing to repair FPGA devices with wear-out faults by precomputing a set of repair circuits that, collectively, can repair a fault found in any logic block of the FPGA. This approach relies on logic placement and routing to create “repair” circuits that avoid specific logic blocks. These repairs can be used when a specific resource has failed. New placement and routing algorithms are proposed for generating such repair circuits. The number of repairs needed to create a complete repair set depends heavily on the utilization of the FPGA resources. The algorithms are tested against several benchmarks and with multiple area constraints for each benchmark. Using this work, on average 20 repair configurations were needed to repair 99% of permanent faults.

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In this dissertation, a novel self-repair approach based on Consensus Based Evaluation (CBE) for autonomous repair of SRAM-based Field Programmable Gate Arrays (FPGAs) is developed, evaluated, and refined. An initial population of functionally identical (same input-output behavior), yet physically distinct (alternative design or place-and-route realization) FPGA configurations is produced at design time. During run-time, the CBE approach ranks these alternative configurations after evaluating their discrepancy relative to the consensus formed by the population. Through runtime competition, faults in the logical resources become occluded from the visibility of subsequent FPGA operations. Meanwhile, offspring formed through crossover and mutation of faulty and viable configurations are selected at a controlled re-introduction rate for evaluation and refurbishment. Refurbishments are evolved in-situ, with online real-time input-based performance evaluation, enhancing system availability and sustainability, creating an Organic Embedded System (OES). A fault tolerance model called N Modular Redundancy with Standby (NMRSB) is developed which combines the two popular fault tolerance techniques of NMR and Standby fault tolerance in order to facilitate the CBE approach. This dissertation develops two of instances of the NMRSB system - Triple Modular Redundancy with Standby (TMRSB) and Duplex with Standby (DSB). A hypothetical Xilinx Virtex-II Pro FPGA model demonstrates their viability for various applications including a 3-bit x 3-bit multiplier, and the MCNC91 benchmark circuits. Experiments conducted on the model iii evaluate the performance of three new genetic operators and demonstrate progress towards a completely self-contained single-chip implementation so that the FPGA can refurbish itself without requiring a PC host to execute the Genetic Algorithm. This dissertation presents results from the simulations of multiple applications with a CBE model implemented in the C++ programming language. Starting with an initial population of 20 and 30 viable configurations for TMRSB and DSB respectively, a single stuck-at fault is introduced in the logic resources. Fault refurbishment experiments are conducted under supervision of CBE using a fitness state evaluation function based on competing outputs, fitness adjustment, and different level threshold. The device remains online throughout the process by which a complete repair is realized with Hamming Distance and Bitweight voting schemes. The results indicate a Hamming Distance TMRSB approach can prevent the most pervasive fault impacts and realize complete refurbishment. Experimental results also show that the Autonomic Layer demonstrates 100% faulty component isolation for both Functional Elements (FEs) and Autonomous Elements (AEs) with randomly injected single and multiple faults. Using logic circuits from the MCNC-91 benchmark set, availability during repair phases averaged 75.05%, 82.21%, and 65.21% for the z4ml, cm85a, and cm138a circuits respectively under stated conditions. In addition to simulation, the proposed OES architecture synthesized from HDL was prototyped on a Xilinx Virtex II Pro FPGA device supporting partial reconfiguration to demonstrate the feasibility for intrinsic regeneration of the selected circuit.

This thesis aims to develop hardware for laboratory in courses such asSwitching Theory at Halmstad University which can help students tounderstand practical applications of the hardware they are studying atuniversity. To achieve this, a printed circuit board (PCB) that simulates trafficintersections has been designed, constructed, and tested.The project consists of four main phases. The first step is to create anequipment list to identify the components needed to meet our goals. Then, theschematic design phase is started using KiCad program for PCB design. Aprinted circuit board is manufactured, and all the components lists in theequipment inventory is carefully soldered. This step completes the secondstage, involving PCB fabrication and component placement. The next step isto program one intersection using an embedded system according to a statemachine and ensure the PCB works properly. For this purpose, a statemachine is developed to describe test conditions and program sequences.

Field-programmable gate arrays (FPGAs) are powerful integrated circuits for low-overhead custom computing needs and design prototyping. Due to the hardware nature of programming an FPGA, finding bugs in a design can be a very challenging process. Signals need to be physically probed and data recorded in real time. This is often done by dedicating some resources on the FPGA itself towards an embedded logic analyzer. This method is effective but can be time and resource consuming. Academic research projects have produced a variety of methods for reducing this difficulty. One option that has previously been unexplored is the use of distributed LUT memory for debug trace buffers, rather than dedicated FPGA BRAM. This dissertation presents a novel, lean embedded logic analyzer that leverages leftover LUT resources on the FPGA for this purpose. Distributed Memory Debug (abbreviated as "DIME Debug") provides some amount of signal visibility into very large (90\%+ LUT utilized) FPGA designs or designs where the programmer requires all available device BRAM, situations in which currently available embedded logic analyzers are likely to fail. The ubiquitous nature of LUTs on FPGAs provides opportunities to insert debug circuitry near signals of interest without disturbing placement of the user design. Using only leftover LUTs for trace buffers allows for effectively no area overhead. The DIME Debug system typically has a critical path delay in the 7-9ns range, which can force non-ideal slower timing constraints on the user design. A simulated annealing based placement algorithm and other optimizations are shown to improve timing closure results from 20-50\% depending on benchmark and probe count. DIME debug can be instrumented into a fully implemented design incrementally using the RapidWright CAD tool, resulting in debug iterations under 15 minutes even for very large benchmarks. Another interesting possibility introduced by the use of memory LUTs for debug trace buffers is preallocating these resources. Setting aside a certain number of LUTs before implementation of the user design leaves them available for incremental debug instrumentation. Experiments with a preallocation scheme show that, with virtually no penalty to the user design, debug critical paths are lowered by approximately 1ns and 2-3X the number of trace buffers can be instrumented into most benchmarks.

Feature detection, description and matching are crucial steps in many computer vision algorithms. These rely on feature descriptors to be able to match image features across sets of images. This paper discusses a hardware implementation and various optimizations of our lab's previous work on the SYnthetic BAsis feature descriptor (SYBA). Previous work has shown that SYBA can offer superior performance to other binary descriptors, such as BRIEF. This hardware implementation on an FPGA is a high throughput and low latency solution, which is critical for applications such as: high speed object detection and tracking, stereo vision, visual odometry, structure from motion, and optical flow. Finally, we compare our solution to other hardware methods. We believe that our implementation of SYBA as a feature descriptor in hardware offers superior image feature matching performance and uses less resources than most binary feature descriptor implementations.

For this thesis the algorithm of a Particle Filter has been partly implemented on a Zynq All-programmable SoC allowing for speed ups of up to 12 times in parts of the code. The implementation is used to track a robot in an environment known by a 2D map. Since some parts have not been implemented in hardware lots of communication is done between the hardware and software parts of the code which creates a performance bottleneck.

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