The increasing threat of Global Navigation Satellite System (GNSS) spoofing attacks necessitates the development of robust defense mechanisms and the testing of potential vulnerabilities. In this project, we present the development and testing of an ultraportable Global Positioning System (GPS) spoofer using an Software Defined Radio (SDR) platform, BladeRF. The spoofer enables users to initiate synchronous spoofing attacks with kilobyte-level files, facilitating synchronous attacks. The project comprises two primary components: an acquisition block based on a serial-search algorithm and a GPS signal simulator. The design emphasizes module reuse, allowing for cost-effective implementation on a relatively small and affordable Field Programmable Gate Arrays (FPGA). This project provides a foundation for both GPS spoofing research and defense algorithm testing, proving the ease of developing a spoofer. / Det ökade hotet från GNSS-förfalskningsattacker kräver utveckling av robusta försvarsmekanismer och testning av potentiella sårbarheter. I det här projektet presenterar vi utvecklingen och testningen av en ultraportabel GPSförfalskare med hjälp av en mjukvarudefinierad radio, BladeRF. Förfalskaren möjliggör att användare kan initiera synkrona förfalskningsattacker med kilobytenivåfiler, vilket underlättar synkrona attacker. Projektet består av två primära komponenter: en samplingsblock baserad på en sekventiell sökalgoritm och en GPS-signalsimulator. Designen betonar återanvändning av moduler, vilket möjliggör kostnadseffektiv implementering på en relativt liten och prisvärd FPGA. Detta projekt ger en grund för både forskning om GPS-förfalskning och testning av försvarsalgoritmer och visar på enkelheten att utveckla en förfalskare.

Systeme der Computer Vision spielen in der Automatisierung vieler Prozesse eine wichtige Rolle. Die wichtigste Aufgabe solcher Systeme ist die Automatisierung des visuellen Erkennungsprozesses und die Extraktion der relevanten Information aus Bildern oder Bildsequenzen. Eine wichtige Komponente dieser Systeme ist die Bildsegmentierung, denn sie bestimmt zu einem großen Teil die Qualitaet des Gesamtsystems. Fuer die Segmentierung von Bildern und Bildsequenzen werden neue Algorithmen vorgeschlagen. Das Konzept der Multiresolution wird als eigenstaendig dargestellt, es existiert unabhaengig von der Wavelet-Transformation. Die Wavelet-Transformation wird zur Verarbeitung von Bildern und Bildsequenzen zu einer 2D- bzw. 3D-Wavelet- Transformation erweitert. Fuer die Segmentierung von Bildern wird der Algorithmus Resolution Mosaic Expectation Maximization (RM-EM) vorgeschlagen. Das Ergebnis der Vorverarbeitung sind unterschiedlich aufgeloesten Teilbilder, das Aufloesungsmosaik. Durch dieses Mosaik lassen sich raeumliche Korrelationen zwischen den Pixeln ausnutzen. Die Verwendung unterschiedlicher Aufloesungen beschleunigt die Verarbeitung und verbessert die Ergebnisse. Fuer die Extraktion von bewegten Objekten aus Bildsequenzen werden neue Algorithmen vorgeschlagen, die auf der 3D-Wavelet-Transformation und auf der Analyse mit 3D-Wavelet-Packets beruhen. Die neuen Algorithmen haben den Vorteil, dass sie sowohl die raeumlichen als auch die zeitlichen Bewegungsinformationen beruecksichtigen. Wegen der geringen Berechnungskomplexitaet der Wavelet-Transformation ist fuer den ersten Segmentierungsschritt Hardware auf der Basis von FPGA entworfen worden. Aktuelle Anwendungen werden genutzt, um die Algorithmen zu evaluieren: die Segmentierung von Magnetresonanzbildern des menschlichen Gehirns und die Detektion von bewegten Objekten in Bildsequenzen von Verkehrsszenen. Die neuen Algorithmen sind robust und fuehren zu besseren Segmentierungsergebnissen. / More and more computer vision systems take part in the automation of various applications. The main task of such systems is to automate the process of visual recognition and to extract relevant information from the images or image sequences acquired or produced by such applications. One essential and critical component in almost every computer vision system is image segmentation. The quality of the segmentation determines to a great extent the quality of the final results of the vision system. New algorithms for image and video segmentation based on the multiresolution analysis and the wavelet transform are proposed. The concept of multiresolution is explained as existing independently of the wavelet transform. The wavelet transform is extended to two and three dimensions to allow image and video processing. For still image segmentation the Resolution Mosaic Expectation Maximization (RM-EM) algorithm is proposed. The resolution mosaic enables the algorithm to employ the spatial correlation between the pixels. The level of the local resolution depends on the information content of the individual parts of the image. The use of various resolutions speeds up the processing and improves the results. New algorithms based on the 3D wavelet transform and the 3D wavelet packet analysis are proposed for extracting moving objects from image sequences. The new algorithms have the advantage of considering the relevant spatial as well as temporal information of the movement. Because of the low computational complexity of the wavelet transform an FPGA hardware for the primary segmentation step was designed. Actual applications are used to investigate and evaluate all algorithms: the segmentation of magnetic resonance images of the human brain and the detection of moving objects in image sequences of traffic scenes. The new algorithms show robustness against noise and changing ambient conditions and gave better segmentation results.

Diese Arbeit befasst sich mit der Entwicklung eines echtzeitfähigen Systems zur Erstellung von Tiefeninformation aus Stereobildpaaren, das in einer Reihe von Anwendungen zur dreidimensionalen Vermessung des Raumes herangezogen werden kann. Als Hauptanwendungsgebiete sind in erster Linie mobile Robotikapplikationen vorgesehen, die sehr strenge Anforderungen sowohl bezüglich des Ressourcenverbrauchs als auch im Hinblick auf die Messeigenschaften und das Laufzeitverhalten stellen. Ein Merkmal des in dieser Arbeit entworfenen Systems ist die in Echtzeit stattfindende Ausführung der verwendeten Algorithmen in Kombination mit sehr guten Messeigenschaften. Das verwendete Stereo-Matching-Verfahren basiert auf einem globalen Ansatz und liefert im Vergleich zu den alternativen echtzeitfähigen Methoden sehr gute Ergebnisse. Im Vordergrund steht dabei der Semi-Global-Matching-Algorithmus. Aufgrund der Komplexität globaler Ansätze finden in Echtzeitapplikationen nur lokale Stereo-Verfahren Verwendung. Lokale Verfahren liefern jedoch im Vergleich zu den globalen Methoden qualitativ schlechte Disparitätskarten. Ein neuer globaler Matching-Algorithmus Efficient-Semi-Global-Matching (eSGM) wird vorgestellt und in das Konzept für mobile Robotikanwendungen umgesetzt. Wegen der begrenzten Ressourcen der realen Hardware wurde eine Weiterentwicklung des eSGM-Algorithmus für die Realisierung genutzt. Abschließend wird das System anhand der drei Kerneigenschaften Laufzeit, Ressourcenverbrauch und Qualität der Tiefeninformation gegenüber den Verfahren nach dem Stand der Technik bewertet. Der in dieser Arbeit vorgestellte FPGA-Ansatz, die eingesetzte Entwurfsmethode und die vorgestellten Algorithmen ermöglichten es, ein leistungsfähiges Stereo-Bildverarbeitungssystem zu entwickeln, das den hohen Anforderungen bezüglich des Laufzeitverhaltens und der Qualität des Ergebnisses gerecht wird. / This work presents a realtime stereo image matching system that takes advantage of a global image matching method. The system is designed to provide depth information for mobile robotic applications. Typical tasks of the proposed system are to assist in obstacle avoidance, SLAM and path planning of mobile robots, that pose strong requirements on the size, energy consumption, reliability, frame rate and quality of the calculated depth map. Current available systems either rely on active sensors or on local stereo-image matching algorithms. The first are only suitable in controlled environments while the second suffer from low quality depth-maps. Top ranking quality results are only achieved by an iterative approach using global image matching and colour segmentation techniques which are computationally demanding and therefore difficult to be executed in real time. Attempts were made to still reach real-time performance with global methods by simplifying the routines but led to degraded depth maps which are at the end almost comparable with local methods. An equally named semi-global algorithm was proposed earlier, that shows both very good image matching results and relatively simple execution at the same time. A memory efficient variant of the Semi-Global Matching algorithm is presented and adopted for an implementation based on reconfigurable hardware that is suitable for real-time operations in the field of robotics. It will be shown that the modified version of the efficient Semi-Global matching method is delivering equivalent result compared to the original algorithm. The complete design has been implemented within a hardware development framework that is also reviewed.

No description available.

Master of Science / Department of Electrical and Computer Engineering / Don M. Gruenbacher / As semiconductor technologies advance, the smallest feature sizes that can be fabricated get smaller. This has led to the development of high density FPGAs capable of supporting high clock speeds, which allows for the implementation of larger more complex designs on a single chip. Over the past decade the technology market has shifted toward mobile devices with low power consumption at or near the top of design considerations. By reducing power consumption in FPGAs we can achieve greater reliability, lower cooling cost, simpler power supply and delivery, and longer battery life. In this thesis, FPGA technology is discussed for the design and commercial implementation of low power systems as compared to ASICs or microprocessors, and a few techniques are suggested for lowering power consumption in FPGA designs. The objective of this research is to implement some of these approaches and attempt to design a low power signal acquisition module. Designing for low power consumption without compromising performance requires a power-efficient FPGA architecture and good design practices to leverage the architectural features. With various power conservation techniques suggested for every stage of the FPGA design flow, the following approach was used in the design process implementation: the switching activity is addressed in the design entry, and synthesis level and software tools are utilized to get an initial estimate of and optimize the design’s power consumption. Finally, the device choice is made based on its features that will enhance the optimization achieved in the previous stages; it is configured and real time board level power measurements are made to verify the implementation’s efficacy

International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / Increasing gate counts in FPGA’s create an option of offering multiple waveform demodulation and modulation within a single transponder transceiver. Differing data rates, channel schemes, and network protocols can be addressed with the flexibility of software-based demodulation and modulation. Increased satellite longevity and reliability are benefits of software-based transceiver design. Newer packaging technology offers additional capability in reducing form factor and weight of a transponder. A review of the challenges in combining each of the above to produce the next generation of transponders is the subject of this paper.

Le projet de recherche s’inscrit dans un contexte d'imagerie moléculaire, où la modalité d'imagerie d'intérêt est la tomographie d'émission par positrons (TEP) appliquée en recherche sur les petits animaux. Afin de permettre l’observation de détails infimes, les plus récents développements sur ce genre de scanner ont constamment amélioré leur résolution spatiale, sans toutefois obtenir les mêmes progrès en terme de sensibilité. Parmi les méthodes étudiées afin de combler cette lacune, la récupération de coïncidences triples à l’aide d'un réseau de neurones artificiels semble être une technique viable. En effet, malgré une dégradation du contraste, celle-ci permet d'améliorer substantiellement la sensibilité de l’image. Cette technique n'est cependant pas prête à être intégrée aux protocoles de recherche, car son application est pour l’instant limitée à un traitement hors ligne des données d'acquisition d'un scanner. En conséquence, la faisabilité d'une telle approche en temps réel n'est donc pas garantie, car le flux de coïncidences d'un scanner est très important et ses ressources de calculs sont limitées. Dans l’intention d'inclure ce gain en sensibilité pendant une acquisition où le traitement est effectué en temps réel, ce projet de recherche propose une implémentation d'un réseau de neurones artificiels au sein d'une matrice de porte programmable (FPGA) pouvant récupérer en temps réel les coïncidences diffuses triples du scanner LabPET, version 4 cm. La capacité de traitement obtenue est 1 087 000 coïncidences triples par seconde en utilisant 23.1% des ressources d'unités logiques d'un FPGA de modèle XC2VP50. Comparativement à un programme équivalent à haute précision sur ordinateur personnel, l’analyse de validité prend la même décision dans 99.9% des cas et la même ligne de réponse est choisie dans 97.9% des cas. Intégrées à l’image, les coïncidences triples permettent une augmentation de sensibilité jusqu’à 39.7%, valeur qui est en deçà [de] celle obtenue des recherches antérieures, mais expliquée par des conditions d'acquisition différente. Au niveau de la qualité de l’image, la dégradation du contraste de 16,1% obtenu est similaire à celle observée antérieurement. En référence à ces résultats, les ressources limitées d'un scanner de tomographie d'émission par positrons sont avérées suffisantes pour permettre l’implémentation d'un réseau de neurones artificiels devant classifier en temps réel les coïncidences triples du scanner. En terme de contributions, l’implémentation en temps réel réalisée pour ce projet confirme la faisabilité de la technique et apporte une nouvelle approche concrète pour améliorer la sensibilité. Dans une autre mesure, la réussite du projet de recherche contribue à faire connaître la technique des réseaux de neurones artificiels dans le domaine de la tomographie d’émission par positrons. En effet, cette approche est pertinente à considérer en guise d'alternative aux solutions traditionnelles. Par exemple, les réseaux de neurones artificiels pourraient effectuer une évaluation correcte du phénomène des coïncidences fortuites.

International Telemetering Conference Proceedings / October 21, 2002 / Town & Country Hotel and Conference Center, San Diego, California / This paper describes an approach to the implementation of an IF sampling digital receiver for low data rate command and telemetry applications in the NASA Goddard Spaceflight Tracking and Data Network (STDN) and Air Force Space-Ground Link System (SGLS). The digital design is targeted for an FPGA-based implementation and was written entirely in VHDL. Several size and clock reduction techniques are described which were utilized due to limited gate-array resources and power. The system-level design architecture is described followed by a discussion of algorithms and performance of critical stages in the receiver chain. Bit error performance of the prototype receiver is also presented. Finally, although this design is specifically targeted for a narrowband command and telemetry application, the methodology forms the basis of a configurable receiver for higher data rate applications.

ITC/USA 2005 Conference Proceedings / The Forty-First Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2005 / Riviera Hotel & Convention Center, Las Vegas, Nevada / The GPS receiver based on software radio technology is a kind of general purpose GPS signal processing platform which makes use of advanced design ideas and advanced design tools nowadays. We used FPGA device and lots of necessary peripherals such as DSP and PCI controller in our design to promote flexibility and practicability effectively. Various fast acquisition means and accurate tracking algorithms could be realized, improved and validated on this platform, besides basic GPS receiver function.

Cyber-Physical Systems theory is a new concept that is about to revolutionize the way computers interact with the physical world by integrating physical knowledge into the computing systems and tailoring such computing systems in a way that is more compatible with the way processes happen in the physical world. In this master’s thesis, Field Programmable Gate Arrays (FPGA) are studied as a potential technological asset that may contribute to the enablement of the Cyber-Physical paradigm. As an example application that may benefit from cyber-physical system support, the Electro-Slag Remelting process - a process for remelting metals into better alloys - has been chosen due to the maturity of its related physical models and controller designs. In particular, the Particle Filter that estimates the state of the process is studied as a candidate for FPGA-based computing enhancements. In comparison with CPUs, through the designs and experiments carried in relationship with this study, the FPGA reveals itself as a serious contender in the arsenal of v computing means for Cyber-Physical Systems, due to its capacity to mimic the ubiquitous parallelism of physical processes. / text