ISIS es una placa madre industrial desarrollada en Chile por Continental Lensa S.A orientada al soporte de SoPCs (Systems on a Programmable Chip) sobre un dispositivo FPGA (Field Programmable Gate Array), integrado con una serie de periféricos on-board. La capacidad de soportar SoPCs basados en el procesador Nios II y el sistema operativo uClinux, en conjunto con diversos núcleos de hardware de propiedad intelectual o IP cores, abre un universo de aplicaciones que abarca desde el control de sistemas, procesamiento digital de señales, y sistemas de radio y televisión digital. ISIS incorpora un conector PMC (PCI Mezzanine Card), que corresponde a una especificación mecánica para sistemas PCI de montaje paralelo y tamaño pequeño, contrario al estándar PCI convencional donde las tarjetas se montan en forma perpendicular. Sin embargo, no es posible controlar dispositivos PCI con la plataforma ISIS sin un adecuado soporte de hardware y software que provea una interfaz de bus acorde a los requerimientos del estándar PCI. El presente trabajo otorga a la plataforma ISIS soporte para conectividad con dispositivos PCI 3.3V 32 bit @ 33 MHz. El trabajo aporta la implementación de un chipset PCI embebido en el dispositivo FPGA, el soporte de software para operación con el sistema operativo uClinux, y una aplicación para control y diagnóstico del hardware. Además, se aporta un nuevo hardware que brinda una solución a la incompatibilidad entre los complejos estándares mecánicos PCI Mezzanine Card y PCI convencional de PC. Uno de los aportes es la implementación del IP core de libre distribución PCI Bridge de Opencores con interfaz de bus Wishbone, en un SoPC con arquitectura de comunicación nativa Avalon System Interconnect Fabric, lo que requiere implementar lógica de adaptación entre dos estándares de interconexión SoC incompatibles. Además, los requerimientos del sistema exigen que el IP core PCI Bridge sea implementado en modo Host, estando disponible solamente con pruebas de operación en modo Guest, lo que implica el desafío de implementar funcionalidades que no cuentan con un proceso de validación. También se desarrolla una capa de software que comunica el hardware PCI con el kernel de Linux, y un programa que permite el control y diagnóstico de los dispositivos presentes en el bus. El presente trabajo se integra como parte fundamental del equipo de radiodifusión digital de tercera generación GSD-21 Exgine. El núcleo de hardware del equipo lo constituye la plataforma ISIS integrada con el dispositivo PCI DUC-II (Next Generation Digital Up Converter), por medio de los sistemas de hardware y software desarrollados. Se obtiene una tasa de transferencia promedio de 14,5 MByte/s para transferencias PCI usando DMA, y una tasa de error de bus igual a cero para 24 horas de operación sin interrupciones del equipo GSD-21.

In state-of-the-art fiber-optics communication systems the fixed forward error correction (FEC) and constellation size are employed. While it is important to closely approach the Shannon limit by using turbo product codes (TPC) and low-density parity-check (LDPC) codes with soft-decision decoding (SDD) algorithm; rate-adaptive techniques, which enable increased information rates over short links and reliable transmission over long links, are likely to become more important with ever-increasing network traffic demands. In this invited paper, we describe a rate adaptive non-binary LDPC coding technique, and demonstrate its flexibility and good performance exhibiting no error floor at BER down to 10(-15) in entire code rate range, by FPGA-based emulation, making it a viable solution in the next-generation high-speed intelligent aggregation networks.

FPGA stands for Field Programmable Gate Array and it is a technology that has been on the rise the last decades. With a decrease in size of the logic elements commercially available products have started to have more built-in functionality in one package and by being reprogrammable makes the system a powerful competitor among its neighbors. FPGA technology in comparison with Digital Signal Processing technology is generally interesting because of the parallelism of the programming that can be made. This allows for more operations in less time. In this thesis a system is developed to control power converters with control signals in high frequency. A previous project is used as a base and a toolchain of new components are implemented to create a new, more generic system. The previous system is evaluated and a new protocol for communication is developed. The toolchain with the necessary control blocks is implemented in Quartus II that includes a timer block, a pulse width modulation block, a PID controller block and a FIR-filter block. The system is used to control a power converter and the result is evaluated.

This work is part of an on-going research project at Virginia Commonwealth University in the field of Unmanned Aerial Vehicles (UAVs). The purpose of this thesis project is to port the previous generation of UAV autopilot from the Atmel FPSLIC platform to the Xilinx MicroBlaze platform in order to provide a test-bed that will accommodate future research projects. The tasks include porting the software from the AVR processor located on the FPSLIC to the MicroBlaze processor and implementing the hardware peripherals in Xilinx FPGA.The UAV equipped with the new autopilot can autonomously navigate through pre-defined waypoints and transmit the collected data back to the ground base station for analysis.

Mémoire numérisé par la Direction des bibliothèques de l'Université de Montréal.

Mémoire numérisé par la Direction des bibliothèques de l'Université de Montréal.

Les avancées dans le domaine de la bioinformatique ont ouvert de nouveaux horizons pour la recherche en biologie et en pharmacologie. Les machines comme les algorithmes utilisées aujourd'hui ne sont cependant plus en mesure de répondre à la demande exponentiellement croissante en puissance de calcul. Il existe donc un besoin pour des plate-formes de calculs spécialisées pour ce types de traitement, qui sauraient tirer partie de l'ensemble des technologie de calcul parallèle actuelles (Grilles, multi-coeurs, GPU, FPGA). Dans cette thèse nous étudions comment l'utilisation d'outils de synthèse de haut niveau peut aider à la conception d'accélérateurs matériels spécialisés massivement parallèles. Ces outils permettent de réduire considérablement les temps de conception mais ne sont pas conçus pour produire des architectures matérielles massivement parallèles efficaces. Les travaux de cette thèse se sont attachés à dégager des techniques de parallélisation, ainsi que les moyens d'exprimer efficacement ce parallélisme, pour des outils de type HLS. Nous avons appliqué ces résultats à une application de bioinformatique connue sous le nom de HMMER. Cet algorithme qui pourrait être un bon candidat à une accélération matérielle est très délicat à paralléliser. Nous avons proposé un schéma d'exécution parallèle original, basé sur une réécriture mathématique de l'algorithme, qui a été suivi par une exploration des schéma d'exécution matériels possible sur FPGA. Ce résultat à ensuite donnée lieu à une mise en œuvre sur un accélérateur matériel et a démontré des facteurs d'accélération encourageants. Les travaux démontre également la pertinence des outils de HLS pour la conception d'accélérateur matériel pour le calcul haute performance en Bioinformatique, à la fois pour réduire les temps de conception, mais aussi pour obtenir des architectures plus efficaces et plus facilement reciblables d'un plateforme à une autre. / The revolutionary advancements in the field of bioinformatics have opened new horizons in biological and pharmaceutical research. However, the existing bioinformatics tools are unable to meet the computational demands, due to the recent exponential growth in biological data. So there is a dire need to build future bioinformatics platforms incorporating modern parallel computation techniques. In this work, we investigate FPGA based acceleration of these applications, using High-Level Synthesis. High-Level Synthesis tools enable automatic translation of abstract specifications to the hardware design, considerably reducing the design efforts. However, the generation of an efficient hardware using these tools is often a challenge for the designers. Our research effort encompasses an exploration of the techniques and practices, that can lead to the generation of an efficient design from these high-level synthesis tools. We illustrate our methodology by accelerating a widely used application -- HMMER -- in bioinformatics community. HMMER is well-known for its compute-intensive kernels and data dependencies that lead to a sequential execution. We propose an original parallelization scheme based on rewriting of its mathematical formulation, followed by an in-depth exploration of hardware mapping techniques of these kernels, and finally show on-board acceleration results. Our research work demonstrates designing flexible hardware accelerators for bioinformatics applications, using design methodologies which are more efficient than the traditional ones, and where resulting designs are scalable enough to meet the future requirements.

The master’s thesis deals with the design of modulator OFDM in the FPGA circuit. The thesis describes basic attributes of modulation OFDM, its pros and cons. With the help of created block level scheme, it describes all the components of the processing of the data signal on its way from the transmitter to the receiver. The Atlys Spartan-6 Development Board has been chosen for the implementation of the modulator. The other part of thesis is the design and realization of the analog-digital interface for the modulator OFDM. The interface consists of PCB, which is connected to the development board using expansion connector. The board is assembled with all the parts required for transmitting the signal as well as consecutive receiving, the description of used solutions is also a part of this master’s thesis. Proper function of both designed parts was verified using hardware co-simulation.

Master´s thesis deals with creating circuit for receiving data from industrial camera. IP Core is designing for FPGA. Theoretical part of the work describes SDI interface, analysis of relevant SMPTE standards and specification of data format. The thesis include general characteristics of multigigabit transceivers. Practical part include VHDL description of SDI receiver. Thesis presents simulations of created circuit, implementation for real application and measurement results for signal transmission over slip ring.

An efficient design dedicated for iterative-multiple-input multiple-output (MIMO) receiver systems is now imperative in our world since data demands are increasing tremendously in wireless networks. This puts a massive burden on the signal processing power especially in small receiver systems where power sources are often shared or limited. This thesis proposes an attractive solution to both the wireless signal processing and the architectural implementation design sides of the problem. A novel algorithm, dubbed the Adaptive Switching Algorithm, is proven to not only save more than a third of the energy consumption in the algorithmic design, but is also able to achieve an energy reduction of more than 50% in terms of processing power when the design is mapped onto state-of-the-art programmable hardware. Simulations are based in MatlabTM using the Monte Carlo approach, where multiple additive white Gaussian noise (AWGN) and Rayleigh fading channels for both fast and slow fading environments were investigated. The software selects the appropriate detection algorithm depending on the current channel conditions. The design for the hardware is based on the latest field programmable gate arrays (FPGA) hardware from Xilinx R , specifically the Virtex-5 and Virtex-7 chipsets. They were chosen during the experimental phase to verify the results in order to examine trends for energy consumption in the proposed algorithm design. Savings come from dynamic allocation of the hardware resources by implementing power minimization techniques depending on the processing requirements of the system. Having demonstrated the feasibility of the algorithm in controlled environments, realistic channel conditions were simulated using spatially correlated MIMO channels to test the algorithm’s readiness for real-world deployment. The proposed algorithm is placed in both the MIMO detector and the iterative-decoder blocks of the receiver. When the final full receiver design setup is implemented, it shows that the key to energy saving lies in the fact that both software and hardware components of the Adaptive Switching Algorithm adopt adaptivity in the respective designs. The detector saves energy by selecting suitable detection schemes while the decoder provides adaptivity by limiting the number of decoding iterations, both of which are updated in real-time. The overall receiver can achieve more than 70% energy savings in comparison to state-of-the-art iterative-MIMO receivers and thus it can be concluded that this level of ‘intelligence’ is an important direction towards a more efficient iterative-MIMO receiver designs in the future.