Significant advanced development in the field of communication has led many designers and healthcare professionals to look towards wireless communication for the treatment of dreadful diseases. Implant medical device offers many benefits, but design of implantable device at very low power combines with high data rate is still a challenge. However, this device does not rely on external source of power. So, it is important to conserve every joule of energy to maximize the lifetime of a device. Choice of modulation technique, frequency band and data rate can be analyzed to maximize battery life. In this thesis work, system level design of FSK and QPSK transmitter is presented. The proposed transmitter is based on direct conversion to RF architecture, which is known for low power application. Both the transmitters are designed and compared in terms of their performance and efficiency. The simulation results show the BER and constellation plots for both FSK and QPSK transmitter.

In recent years, the development of power line communication and relational application is gradually attracted much attention. The use of power line system is able to achieve home network automation, automatic meter reading, and demand supply management, so it can be a great help for the current emphasis on energy conservation ideas. Therefore, many international organizations and national programs involve in researches. The signal is vulnerable to the environment causing data error in the power line transmission, so that we reduce the use of power line communication. For making great application of power line system, the main purpose of the thesis is to study that ensure the data accuracy, integrity and security through power line transmission. Therefore, we designed the digital chip for power line communication. We achieve the signal transmission with the half-duplex ability through power line by digital chip designing and solve error problems about transmitting data. By designing the modules of digital circuit, the chip can encrypt/decrypt data, correct error-bits of data, detect accuracy of data, process control signals, and modulate/demodulate signals. The purpose is for increasing data accuracy in PLC transmission. The chip design adopts TSMC 0.18£gm process as full digital circuits and applies to the energy meter management.

This thesis develops a power line carrier(PLC) communication module using FSK modulation technology by integration of PLC chip, with various hardware circuits such as DSP, signal coupling and amplifier circuits, filter. The communication performance and conduction EMI tests and executed for the communication module developed. The PLC module is then applied for appliance control of commercial customers to fulfill the demand response function for energy conservation by reducing the summer peak loading. Besides sending the load control command from central station in the smart grid, the power consumption of various appliances can also be collected and transmitted back to the control station via two way communication with the PLC communication module. Finally, the broadband PLC (BPLC) is applied for the CCTV supervision in system to support asset management of distribution room to prevent the power equipment from steal. With the remote control of light brightness and CCTV lens with high data transmission rate provided, the communication performance of PLC can therefore be verified in this study.

The paper focuses on the design and implementation of the base-band basic receiving functions, for a binary CP-FSK demodulator pilot study, as independent modules of a complete Reconfigurable Data-Link (RDL). A model-based approach and Software Defined Radio (SDR) paradigm are used for the design. The implementation will be executed on Field-Programmable Gate Array (FPGA) based hardware.

This thesis deals with designing and implementing autonomous decoder for RTTY communication. Theoretical part of the thesis deals with researching the RTTY technology and FSK modulation, which it uses, focusing mainly on the methods of demodulation. Next part of the thesis compares suitability of available platforms. Practical part of the thesis describes the design and implementation of circuit board, firmware and computer application. The device is using STM32 microcontroller. Firmware was developed in C++ using Arduino. The computer application was created by using C\# and WPF. 3 methods of FSK demodulations were implmented. One is using a FFT algorithm. Other two calculate frequency based on the period of square signal.

The purpose of this thesis is to design FSK modem for Packet communication. In accordance with accessible literature was constructed functioning circuit schema and subsequently there was constructed a motherboard which is mainly assembled from SMD technology. It makes this modem mobile and very easy usable in terrain. Modem communicates with PC via USB bus. Also this bus is used as power source for this device. Communication between modem and PC is realized by KISS protocol and connection with tranciever is realized by AX.25 protocol.

International Telemetering Conference Proceedings / October 28-31, 1996 / Town and Country Hotel and Convention Center, San Diego, California / Aerospace Report No. TOR-0059(6110-01)-3, section 1.3.3 outlines the design and performance requirements of SGLS (Space Ground Link Subsystem) uplink services equipment. This modulation system finds application in the U.S. Air Force satellite uplink commanding system. The SGLS signal generator is specified as an FSK (Frequency Shift Keyed)/AM (Amplitude Modulation)/PM (Phase Modulation) sub-carrier modulator. GDP Space Systems has implemented, on a single 6U-VME card, a SGLS signal generator. The modulator accepts data from several possible sources and uses the data to key one of three FSK tone frequencies. This ternary FSK signal is amplitude modulated by a synchronized triangle wave running at one half the data rate. The FSK/AM signal is then used to phase modulate a tunable HF (High-Frequency) sub-carrier. A digital design approach and the availability of integrated circuits with a high level of functionality enabled the realization of a SGLS signal generator on a single VME card. An analog implementation would have required up to three rack-mounted units to generate the same signal. The digital design improve performance, economy and reliability over analog approaches. This paper describes the advantages of a digital FSK/AM/PM modulation method, as well as DDS (Direct Digital Synthesis) and digital phase-lock techniques.

<p>This master thesis is as a final project in the Division of Computer Engineering at the Department of Electrical of Engineering, Linköping University, Sweden. The purpose of the project is to set up a baseband behavioral model for a Bluetooth system based on standards. In the model, synchronization in demodulation part has been focused on. Simulation results are analyzed later in the report to see how the method in demodulation works. Some suggestions and future works for receiver are provided to improve the performances of the model.</p>

<p>This thesis is one part of a overall task of designing a module for frequency shift keying (FSK) to be used in an Ultra Wide Band (UWB) system. The FSK system has a Direct Digital Synthesizer (DDS) and Digital-to-Analog (DAC). The DACs differential current signals are directly fed to a RF (Radio Frequency) unit that generates the UWB RF signal.</p><p>The focus of this thesis is on DAC while the DDS is developed in VHDL as another thesis work. This thesis demonstrates a low-power, ultra wide band 10 bit DAC with an update frequency of 24 MSPS(Mega Samples Per Second). The DAC uses a L-fold linear interpolation architecture. It includes a 16-tap voltage controlled delay line and a 10 bit binary-weighted DAC with a time interleaved structure. The linear interpolation technique improves the attenuation of mirror components and also reduces the glitch. This helps to relax the analog filter requirements and sometimes an off chip capacitor is enough as low pass filter. The attenuation of image components is doubled in decibels(dB) compared with that of conventional DAC.</p><p>In this work various DAC architectures are studied. The current-steering DAC is chosen due to its high speed and high resolution. A binary weighted architecture is chosen to reduce the digital circuits. This helped in reducing the power consumption. The design and simulation is done with help of Cadence. The layout is done in Cadence Virtuoso and the DDS is integrated with the DAC. The chip is to be manufactured in 130 nm CMOS process.</p>

This thesis is one part of a overall task of designing a module for frequency shift keying (FSK) to be used in an Ultra Wide Band (UWB) system. The FSK system has a Direct Digital Synthesizer (DDS) and Digital-to-Analog (DAC). The DACs differential current signals are directly fed to a RF (Radio Frequency) unit that generates the UWB RF signal. The focus of this thesis is on DAC while the DDS is developed in VHDL as another thesis work. This thesis demonstrates a low-power, ultra wide band 10 bit DAC with an update frequency of 24 MSPS(Mega Samples Per Second). The DAC uses a L-fold linear interpolation architecture. It includes a 16-tap voltage controlled delay line and a 10 bit binary-weighted DAC with a time interleaved structure. The linear interpolation technique improves the attenuation of mirror components and also reduces the glitch. This helps to relax the analog filter requirements and sometimes an off chip capacitor is enough as low pass filter. The attenuation of image components is doubled in decibels(dB) compared with that of conventional DAC. In this work various DAC architectures are studied. The current-steering DAC is chosen due to its high speed and high resolution. A binary weighted architecture is chosen to reduce the digital circuits. This helped in reducing the power consumption. The design and simulation is done with help of Cadence. The layout is done in Cadence Virtuoso and the DDS is integrated with the DAC. The chip is to be manufactured in 130 nm CMOS process.