O planejamento de experimentos em sistemas computacionais não é uma tarefa trivial, pois envolve diversas etapas tais como, o planejamento propriamente dito, a execução dos experimentos e a análise dos resultados. A definição e a utilização de metodologias adequadas para cada uma destas etapas facilita a obtenção dos resultados de um experimento em um sistema computacional. Neste trabalho são apresentados mecanismos para auxiliar o planejamento e execução de experimentos em sistemas orientados a serviços. O planejamento de experimento é realizado a partir de um modelo baseado nos conjuntos de entradas comuns a arquiteturas orientadas a serviço. A execução deste planejamento é feita em um ambiente colaborativo real, a qual auxilia a identificação de gargalos que não estão presentes em simulações ou modelos analíticos. Um estudo de caso aplicado na arquitetura WSARCH, possibilitou avaliar seu desempenho e identificar problemas de configuração / The design of experiments in computational systems is not a trivial task as it involves several steps such as planning and execution of the experiments and the analyse of the results. The use of appropriate methodologies for each of these steps makes it easier obtain the experiment results of a computer system. In this dissertation, mechanisms to assist the planning and execution of experiments in service-oriented systems are presented. The planning of the experiment is made according to a model based on a set of common entries for service-oriented architectures. The experiment execution is performed in a real collaborative environment, which helps to identify bottlenecks that are not found in simulations or analytical models. A study case applied in WSARCH architecture, enables to evaluate the performance and identify configuration problems

De nos jours, les mémoires embarquées sont les composants les plus denses dans les "System-On-Chips" (SOCs), représentant actuellement plus que 90% de leur superficie totale. Parmi les différents types de mémoires, les SRAMs sont très largement utilisées dans la conception des SOCs, particulièrement en raison de leur haute performance et haute densité d'intégration. En revanche, les SRAMs conçues en utilisant des technologies submicroniques sont devenus les principaux contributeurs de la consommation d'énergie globale des SOCs. Par conséquent, un effort élevé est actuellement consacré à la conception des SRAMs à faible consommation. En plus, en raison de leur structure dense, les SRAMs sont devenus de plus en plus susceptibles aux défauts physiques comparativement aux autres blocs du circuit, notamment dans les technologies les plus récentes. Par conséquent, les SRAMs se posent actuellement comme le principal détracteur du rendement des SOCs, ce qui cause la nécessité de développer des solutions de test efficaces ciblant ces dispositifs.Dans cette thèse, des simulations électriques ont été réalisées pour prédire les comportements fautifs causés par des défauts réalistes affectant les blocs de circuits spécifiques aux technologies SRAM faible consommation. Selon les comportements fautifs identifiés, différents tests fonctionnels, ainsi que des solutions de tests matériels, ont été proposés pour détecter les défauts étudiés. Par ailleurs, ce travail démontre que les circuits d'écriture et lecture, couramment incorporés dans les SRAMs faible consommation, peuvent être réutilisés pour augmenter le stress dans les SRAMs lors du test, ce qui permet d'améliorer la détection des défauts affectant la mémoire. / Nowadays, embedded memories are the densest components within System-On-Chips (SOCs), accounting for more than 90% of the overall SOC area. Among different types of memories, SRAMs are still widely used for realizing complex SOCs, especially because they allow high access performance, high density and fast integration in CMOS designs. On the other hand, high density SRAMs designed with deep-submicrometer technologies have become the main contributor to the overall SOC power consumption. Hence, there is an increasing need to design low-power SRAMs, which embed mechanisms to reduce their power consumption. Moreover, due to their dense structure, SRAMs are more are more prone to defects compared to other circuit blocks, especially in recent technologies. Hence, SRAMs are arising as the main SOC yield detractor, which raises the need to develop efficient test solutions targeting such devices.In this thesis, failure analysis based on electrical simulations has been exploited to predict faulty behaviors caused by realistic defects affecting circuit blocks that are specific to low-power SRAMs, such as power gating mechanisms and voltage regulation systems. Based on identified faulty behaviors, efficient March tests and low area overhead design for testability schemes have been proposed to detect studied defects. Moreover, the reuse of read and write assist circuits, which are commonly embedded in low-power SRAMs, has been evaluated as an alternative to increase stress in the SRAM during test phase and then improve the defect coverage.

Compte tenu de la complexité des circuits intégrés de nos jours et des nœuds technologiques qui ne cessent pas de diminuer, être au rendez-vous avec les demandes de design, test et fabrication des dispositifs de haute qualité est devenu un des plus grands défis. Avoir des circuits intégrés de plus en plus performants devrait être atteint tout en respectant les contraintes de basse consommation, de niveaux de fiabilité demandés, de taux de défauts acceptables ainsi que du bas coût. Avec ce fascinant progrès de l’industrie des semi-conducteurs, les processus de fabrication sont devenus de plus en plus difficile à contrôler, ce qui rend les puces électroniques de nos jours plus disposés aux défauts physiques. Le test était et restera l’unique solution pour lutter contre l’occurrence des défauts de fabrication ; même il est devenu un facteur prédominant dans le coût totale de fabrication des circuits intégrés. Même si des solutions de test, qui existent déjà, étaient capables de satisfaire ce fameux compromis coût-qualité ces dernières années, il arrive d’observer encore des mécanismes de défauts malheureusement incontrôlables. Certains sont intrinsèquement reliés au processus de fabrication en lui-même. D’autres reviennent sans doute aux pratiques de test et surtout quand on analyse le taux de défauts détectés et le niveau de fiabilité atteint.L’objectif principal de cette thèse est d’implémenter des stratégies de test robustes et efficaces qui répondent aux lacunes des techniques de tests classiques et qui proposent des modèles de fautes plus réalistes et répondent au mieux aux attentes des fournisseurs. Dans l’objectif d’améliorer l’efficacité de test en termes de coût, capacité de couverture de faute, nous présentons divers contributions significatives qui touchent différents domaines entre-autres le test sur le terrain, les tests à hautes fréquences sous contraintes de puissance et finalement le test des chaines de scan.La partie majeure de cette thèse était consacrée pour le développement de nouvelles techniques de tests fonctionnels ciblant les systèmes à processeurs.Les méthodologies appliquées couvrent les problèmes de test sur terrain aussi bien que les problèmes de test de fabrication. Dans le premier cas, la techniques adoptée consiste à fusionner et compacter un ensemble initial de programmes fonctionnels afin d’atteindre une couverture de faute satisfaisante tout en respectant les contraintes du test sur terrain (temps de test réduit et ressource mémoire limitée). Cependant dans le deuxième cas, comme nous avons assez d’informations sur la structure du design, nous proposons un nouveau protocole de test qui va exploiter l’architecture de test existante. Dans ce contexte, nous avons validé et confirmé la relation complémentaire qui joint le test fonctionnel avec le test structurel. D’autres part, cette prometteuse approche assure un test qui respecte les limites de la consommation fonctionnelle et donc une fiabilité meilleure.La dernière contribution de cette thèse accorde toute l’attention à l’amélioration de test de la structure DFT « Design For Test » la plus utilisée qui est la chaîne de scan. Nous présentons dans cette contribution une approche de test qui cible les défauts physiques au sein de la cellule en elle-même.Cette approche représente une couverture de défauts meilleure et une longueur de test plus réduit si nous la comparons avec l’ATPG classique ciblant les mêmes défauts « Intra-cell defect ATPG ».Comme résultat majeur de cette efficace solution de test, nous avons observé une amélioration de 7.22% de couverture de défaut accompagné d’une réduction de 33.5% du temps de test en comparaison avec la couverture et le temps du test atteints par le « Cell-awer ATPG ». / In light of the aggressive scaling and increasing complexity of digital circuits, meeting the demands for designing, testing and fabricating high quality devices is extremely challenging.Higher performance of integrated circuits needs to be achieved while respecting the constraints of low power consumption, required reliability levels, acceptable defect rates and low cost. With these advances in the SC industry, the manufacturing process are becoming more and more difficult to control, making chips more prone to defects.Test was and still is the unique solution to cover manufacturing defects; it is becoming a dominant factor in overall manufacturing cost.Even if existing test solutions were able to satisfy the cost-reliability trade-off in the last decade, there are still uncontrolled failure mechanisms. Some of them are intrinsically related to the manufacturing process and some others belong to the test practices especially when we consider the amount of detected defects and achieved reliability.The main goal of this thesis is to implement robust and effective test strategies to complement the existing test techniques and cope with the issues of test practices and fault models. With the objective to further improve the test efficiency in terms of cost and fault coverage capability, we present significant contributions in the diverse areas of in-field test, power-aware at-speed test and finally scan-chain testing.A big part of this thesis was devoted to develop new functional test techniques for processor-based systems. The applied methodologies cover both in-field and end-of manufacturing test issues. In the farmer, the implemented test technique is based on merging and compacting an initial functional program set in order to achieve higher fault coverage while reducing the test time and the memory occupation. However in the latter, since we already have the structure information of the design, we propose to develop a new test scheme by exploiting the existing scan chain. In this case we validate the complementary relationship between functional and structural testing while avoiding over as well under-testing issues.The last contribution of this thesis deals with the test improvement of the most used DFT structure that is the scan chain. We present in this contribution an intra-cell aware testing approach showing higher intra-cell defect coverage and lower test length when compared to conventional cell-aware ATPG. As major results of this effective test solution, we show that an intra-cell defect coverage increase of up to 7.22% and test time decrease of up to 33.5 % can be achieved in comparison with cell-aware ATPG.

O planejamento de experimentos em sistemas computacionais não é uma tarefa trivial, pois envolve diversas etapas tais como, o planejamento propriamente dito, a execução dos experimentos e a análise dos resultados. A definição e a utilização de metodologias adequadas para cada uma destas etapas facilita a obtenção dos resultados de um experimento em um sistema computacional. Neste trabalho são apresentados mecanismos para auxiliar o planejamento e execução de experimentos em sistemas orientados a serviços. O planejamento de experimento é realizado a partir de um modelo baseado nos conjuntos de entradas comuns a arquiteturas orientadas a serviço. A execução deste planejamento é feita em um ambiente colaborativo real, a qual auxilia a identificação de gargalos que não estão presentes em simulações ou modelos analíticos. Um estudo de caso aplicado na arquitetura WSARCH, possibilitou avaliar seu desempenho e identificar problemas de configuração / The design of experiments in computational systems is not a trivial task as it involves several steps such as planning and execution of the experiments and the analyse of the results. The use of appropriate methodologies for each of these steps makes it easier obtain the experiment results of a computer system. In this dissertation, mechanisms to assist the planning and execution of experiments in service-oriented systems are presented. The planning of the experiment is made according to a model based on a set of common entries for service-oriented architectures. The experiment execution is performed in a real collaborative environment, which helps to identify bottlenecks that are not found in simulations or analytical models. A study case applied in WSARCH architecture, enables to evaluate the performance and identify configuration problems

[pt] Esta dissertação apresenta uma solução para a geração e execução automática de testes funcionais a partir da descrição textual de casos de uso, visando verificar se determinada aplicação atende aos requisitos funcionais definidos por esta documentação. A ferramenta construída é capaz de gerar casos de teste semânticos valorados, transformá-los em código-fonte (para Java Swing e os frameworks de teste TestNG e FEST, na versão atual), executá-los, coletar os resultados e analisar se os casos de uso da aplicação atendem ou não a estes requisitos. Dentre os principais diferenciais da solução construída estão a cobertura de cenários de teste que envolvem múltiplos casos de uso, a cobertura de cenários envolvendo recursão, a possibilidade da definição de regras de negócio sobre dados existentes em bancos de dados de teste, a geração automática dos valores fornecidos nos testes e a geração de testes funcionais semânticos, num formato independente de linguagem de programação e frameworks de teste. / [en] This master s dissertation presents a solution for the automatic generation and execution of functional tests based on the textual use case description and aims to verify whether certain application matches its functional requirements defined by this documentation. The constructed tool is capable of generating valued semantic test cases, of transforming them into source code (for Java Swing and the TestNG and FEST frameworks, in the current version), of executing them, of collecting the results and of analyzing whether the application s use cases matches (or not) its requirements. The solution main differentials includes the coverage of test scenarios that involves more than one use case, the coverage of scenarios containing recursive flows, the possibility of defining business rules using data existing in test databases, as well as the automatic generation of test values, and the generation of semantic functional tests in a format independent of programming languages and frameworks.

In this study we examined dynamic visual acuity as a functional testing of the vestibulo- ocular reflex. Two groups were examined: 22 healthy seniors and 22 healthy young people as controls. We used two types of situations for testing: while walking on a treadmill at a speed of 2, 4 and 5 kmph, and with a subject's head passively moved in yaw and pitch plane. Visual acuity was measured with optotype charts (for the walking test it was a standard Snellen optotype chart at 6 m distance, for the test of head moves it was a Jaeger chart at 30 cm distance). The values obtained in these ways we related to values of a subject's static visual acuity, measured in the same conditions, just before the dynamic situations were examined. We found significant difference of dynamic visual acuity in senior group within each condition tested. We also found a significant decline as for difference of dynamic visual acuity in the senior group compared to young subjects - in the walking test at 4 and 5 kmph and in both head-moving conditions. These results indicate age-related impairment in function of vestibulo-ocular reflex. Based on our results, the test of passive head moves appears to be more suitable for ordinary clinical examination of dynamic visual acuity.

The topic of this thesis is the issue of software testing. The thesis places main emphasis on tools to support test management, manual and automated functional testing and last but not least the tools for defect tracking. The aim of this thesis is introduce readers with software testing, especially with tools that can be used to support testing. The aim is offer an overview of the basic commercial and freely distributed tools for test management, manual testing, automated functional testing and defect tracking. Another aim is design criteria that simplify selection of tool. The second aim of this thesis is practical example of the configuration and description of the basic work with tools IBM Rational - ClearQuest, ClearCase, Manual Tester and Functional Tester. The aims of this thesis were achieved by studying available sources and by own practical experience with the tools to support testing. The contribution of this thesis lies in the characteristics of the selected tools to support testing and especially in design of criteria by which tools can be selected. The last part of thesis provides practical instruction how to configure and work with the tools to support testing of IBM Rational. The thesis is conceived in three main parts. The first part attends to basic terms, which can be found in the area of testing, and to overview of types of tests. There are also described two most famous life-cycle models and methodology RUP. The second part attends to overview of tools to support testing, attention is given to areas: test management, manual testing, defect tracking, and automated functional testing. For each category of tools has been defined criteria according to which tools can be selected. The last part attends to practical example of setting and basic work with the selected tools to support testing of IBM Rational.

Goal of this thesis is to verify functions of hydraulic manifolds from new supplier, measure characteristics of pressure loss relative to flow rate and for proportional blocks also characteristics of flow rate relative to control voltage at constant inlet pressure. Verification will be carried out with proportional manifolds and on/off manifolds with different failure functions.

The diploma thesis is focused on an experimental design of low-noise asphalt mixtures. The theoretical part describes the problems of noise and methods for noise measurements. There are also specified the characteristics of various low-noise asphalt mixtures. The practical part addresses the experimental design of SMA 8 LA. Subsequently, the mixture is exposed to functional testing and the results are afterwards compared with the conventional type of stone mastix asphalt SMA 8 S. The second part is focused primarily on an experimental mixture design of a specific asphalt mixture type - coated macadam. There is especially solved the issue ofbinder drainage and the proportion of cracked grains during the compaction. The advantage of this mixture is the lower price demands cause by lower binder content and a smaller amount of fine aggregate. This mixture should be used as a base layer for low-loaded (traffic) roads. In the conclusion are thereafter evaluated the knowledge and the experience with the testing and designing of individual mixtures gained during the testing.

The MIST(MIniature Student saTellite) project is a 3U CubeSat developed by student teams at KTH Royal Institute of Technology in Stockholm. One of the fundamental systems of the satellite is the Attitude Determination and Control System (ADCS), re sponsible for estimating and correcting the satellite’s orientation using magnetic fields and sun sensors. This final degree work belongs to the MIST functional test team. It focuses on building a test environment that verifies that all ADCS components will be have as expected once the satellite is in orbit. This thesis focuses on creating a test framework that can be used to verify the operation of the ADCS. This test framework is composed of several hardware and software components developed to be reliable and flexible, so it can be adapted to verify the behavior of other systems on the satel lite by other teams in the future. The value of this test framework is demonstrated by setting up a HardwareIntheLoop (HIL) simulation of the ADCS in which real flight hardware is used along with other hardware and software components to create a test scenario as close as possible to the orbit. / MIST­projektet (MIniature Student saTellite) är en 3U CubeSat som utvecklats av studentgrupper vid Kungliga tekniska högskolan (KTH) i Stockholm. Ett av satellitens grundläggande system är Attitude Determination and Control System (ADCS), som ansvarar för att uppskatta och korrigera satellitens orientering med hjälp av magnetfält och solsensorer. Det här examensarbetet hör till MIST:s funktionstestgrupp. Det fokuserar på att bygga en testmiljö som verifierar att alla ADCS-­komponenter kommer att bete sig som förväntat när satelliten väl är i omloppsbana. Det här examensarbetet fokuserar på att skapa en testram som kan användas för att verifiera ADCS:s funktion. Testramen består av flera hardware och software komponenter som utvecklats för att vara tillförlitliga och flexibla, så att den kan anpassas för att verifiera beteendet hos andra system på satelliten av andra team i framtiden. Värdet av denna testram demonstreras genom att man sätter upp en HIL­simulering (Hardware­In­the­Loop) av ADCS där riktig flygmaskinvara används tillsammans med andra hardware och software komponenter för att skapa ett testscenario som ligger så nära omloppsbanan som möjligt.