Thesis (M.S.) University of Missouri-Columbia, 2006. / The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file viewed on (June 26, 2007) Includes bibliographical references.

Thesis (Ph.D.)--University of Wyoming, 2008. / Title from PDF title page (viewed on July 13, 2009). Includes bibliographical references (p. 104-107).

Tolerance analysis is a major link between design and manufacturing. An assembly or a part should be designed based on its functions, manufacturing processes, desired product quality, and manufacturing cost. Assembly tolerance analysis performed at the design stage can reduce potential manufacturing and assembly problems. Several commonly used assembly tolerance analysis models and their limitations are reviewed in this research. Also, a new assembly tolerance analysis model is developed to improve the limitations of the existing assembly tolerance analysis models. The new model elucidates the impact of the flatness symbol (one of the Geometric Dimensioning and Tolerancing (GD&T) specification symbols) and reduces design variables into simple mathematical equations. The new model is based on beta distribution of part dimensions. In addition, a group of manufacturing variables, including quality factor, process tolerance, and mean shift, is integrated in the new assembly tolerance analysis model. A computer integrated system has been developed to handle four support systems for the performance of tolerance analysis in a single computer application. These support systems are: 1) the CAD drawing system, 2) the Geometric Dimensioning and Tolerancing (GD&T) specification system, 3) the assembly tolerance analysis model, and 4) the tolerance database operating under the Windows environment. Dynamic Data Exchange (DDE) is applied to exchange the data between two different window applications, resulting in improvement of information transfer between the support systems. In this way, the user is able to use this integrated system to select a GD&T specification, determine a critical assembly dimension and tolerance, and access the tolerance database during the design stage simultaneously. Examples are presented to illustrate the application of the integrated tolerance analysis system. / Graduation date: 1995

Thesis (Ph. D.)--West Virginia University, 2009. / Title from document title page. Document formatted into pages; contains xiv, 118 p. : ill. (some col.). Includes abstract. Includes bibliographical references (p. 109-118).

Thesis (Ph. D.)--West Virginia University, 2006. / Title from document title page. Document formatted into pages; contains xii, 132 p. : ill. (some col.). Includes abstract. Includes bibliographical references (p. 123-128).

In this thesis, an IGBT-based DC/DC converter employing an internal inductor-capacitor-inductor (LCL) passive circuit is investigated in DC grid under fault conditions. It is concluded that a range of converter parameters exist which will give DC fault current magnitudes close to rated currents. Steady state and transient fault responses are investigated in depth. The converter is modelled on PSCAD platform under fault operation and the simulation results verify the analytical studies. LCL DC hub is an extension of DC/DC converter to multiple ports with capability of limiting the propagation of DC faults in a DC grid. Analytical mathematical equations for steady state fault currents are derived. A state space model of the hub is introduced for transient fault study. The hub is able to interconnect multiple DC cables at different voltage levels and act as DC substation for DC grid. The designed hub also has the ability to maintain the current within the order of its rated value without additional protection even for the worst case fault. The analytical study results are confirmed by detailed simulation on PSCAD. Based on the good performance of the LCL DC hub under DC faults, a DC grid topology with protection system employing LCL DC hub is proposed and investigated in this thesis. The advantage and feasibility of this method in DC fault protection is investigated based on the developed grid model. The DC grid protection systems are proposed and analysed in depth under several DC fault scenarios. The PSCAD simulation results under a range of DC fault scenarios on various locations are shown. These results confirm significance of the proposed DC grid protection system and advantages of this proposed topology in fault isolation.

To ensure that a system is robust and will continue operation even when facing disruptive or traumatic events, we have created a methodology for system architects and designers which may be used to locate risks and hazards in a design and enable the development of more robust and resilient system architectures. It uncovers design vulnerabilities by conducting a complete exploration of a systems’ component operational state space by observing the system from multi-dimensional perspectives and conducts a quantitative design space analysis by means of probabilistic risk assessment using Bayesian Networks. Furthermore, we developed a tool which automated this methodology and demonstrated its use in an assessment of the OCTT PHM communication system architecture. To boost the robustness of a wireless communication system and efficiently allocate bandwidth, manage throughput, and ensure quality of service on a wireless link, we created a wireless link management architecture which applies sensor fusion to gather and store platform networked sensor metrics, uses time series forecasting to predict the platform position, and manages data transmission for the links (class based, packet scheduling and capacity allocation). To validate our architecture, we developed a link management tool capable of forecasting the link quality and uses cross-layer scheduling and allocation to modify capacity allocation at the IP layer for various packet flows (HTTP, SSH, RTP) and prevent congestion and priority inversion. Wireless sensor networks (WSN) are vulnerable to a plethora of different fault types and external attacks after their deployment. To maintain trust in these systems and increase WSN reliability in various scenarios, we developed a framework for node fault detection and prediction in WSNs. Individual wireless sensor nodes sense characteristics of an object or environment. After a smart device successfully connects to a WSN’s base station, these sensed metrics are gathered, sent to and stored on the device from each node in the network, in real time. The framework issues alerts identifying nodes which are classified as faulty and when specific sensors exceed a percentage of a threshold (normal range), it is capable of discerning between faulty sensor hardware and anomalous sensed conditions. Furthermore we developed two proof of concept, prototype applications based on this framework. / Includes bibliography. / Dissertation (Ph.D.)--Florida Atlantic University, 2013.

As device scaling continues, process variability and defect densities are becoming increasingly challenging for circuit designers to contend with. Variability reduces timing margins, making it difficult and time consuming to meet design specifications. Defects can cause degraded performance or incorrect operation resulting in circuit failure. Consequently test times are lengthened and production yields are reduced. This work assess the combination of two concepts, self-timed asynchronous design and fault tolerance, as a possible solution to both variability and defects. Asynchronous design is not as sensitive to variability as synchronous, while fault tolerance allows continued functional operation in the presence of defects. GasP is a self-timed asynchronous design that provides high performance in a simple circuit. Quadded Logic, is a gate level fault tolerant methodology. This study presents Quadded GasP, a fault tolerant asynchronous design. This work demonstrates that Quadded GasP circuits continue to function within performance expectations when faults are present. The increased area and reduced performance costs of Quadded GasP area also evaluated. These results show Quadded GasP circuits are a viable option for managing process variation and defects. Application of these circuits will provide decreased development and test times, as well as increased yield.

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

Thesis (M.S.)--Rochester Institute of Technology, 2009. / Typescript. Includes bibliographical references (leaves