Untestable faults in circuits are defects/faults for which there exists no test pattern that can either excite the fault or propagate the fault effect to an observable point, which could be either a Primary output (PO) or a scan flip-flop. The current state-of-the-art automatic test pattern generators (ATPGs) spend a lot of time in trying to generate a test sequence for the detection of untestable faults, before aborting on them, or identifying them as untestable, given enough time. Thus, it would be beneficial to quickly identify faults that are redundant/untestable, so that tools such as ATPG engines or fault simulators do not waste time targeting these faults. Our work focuses on the identification of untestable faults at low cost in terms of both memory and execution time. A powerful and memory efficient implication engine, which is used to identify the effect(s) of asserting logic values in a circuit, is used as the basic building block of our tool. Using the knowledge provided by this implication engine, we identify untestable faults using a fault independent, conflict based analysis. We evaluated our tool against several benchmark circuits (ISCAS '85, ISCAS '89 and ISCAS '93), and found that we could identify considerably more untestable faults in sequential circuits compared to similar conflict based algorithms which have been proposed earlier. / Master of Science

Folding prior to thrust-sheet emplacement is proposed to explain presence of overturned synclines in the footwalls of many thrust-faults in the Appalachian foreland fold- and thrust-belt of southwest Virginia. Investigation of relations in the footwalls of the Saltville and St. Clair thrust-sheets near the Southern-Central Appalachian juncture indicates presence of at least two distinct types of footwall structures: 1)isolated forelimbs of thrust-truncated asymmetric ramp-generated anticlines, and 2)areally extensive overturned subthrust synclines. Mesoscopic fabric data and strain states indicate rotation of bedding by folding prior to thrust-sheet emplacement rather than drag folding during thrusting. Low angles between bedding and cleavage planes and low strain values on the back limbs of folds at thrust terminations (Sinking Creek anticline) and in hangingwall strata seems to indicate folding was largely accomplished by flexural flow in units of relatively low mechanical strength. / M.S.

Reprocessing of Appalachian Ultradeep Core Hole (ADCOH) southern Appalachian seismic reflection data was focused on improving the reflection imaging and hence interpretability of seismic signatures previously interpreted as duplexes created by thrust stacking of thin beds of Paleozoic shelf strata. The reprocessed data are used to determine a more unique depth domain geometry for one of the proposed duplexes. Reprocessed data are partially improved through an increase in both stacking velocity coverage and datum statics velocity coverage as well as an appropriate use of residual statics. Interpretability increases from the improvement in resolution and the consideration of geologic strike direction relative to profile direction. Initial shotpoint ray trace modeling shows the chaotic nature of raypaths and some of the problems associated with the imaging of reflections when complex geology is involved. Data reprocessing and two-dimensional ray trace modeling yield results which suggest that the studied seismic signature is part of a broad hinterland-dipping duplex. At the trailing edge of the duplex itself beds appear to be successively fault truncated, perhaps explaining the increased amplitude and reflectivity in this zone. The truncations result in a wedge-shaped geometry that resembles the trailing edge of an antiformal stack duplex. The improved data also show 1) a shallow band of reflections that correlate with the Shope Fork and Chunky Gal Mountain faults within the Blue Ridge allochthon, 2) thrust ramping initiated by basement faulting that extends only a short distance into the overlying sedimentary strata, 3) a more highly faulted Grenville basement surface and, 4) almost intact Paleozoic shelf strata (?) being carried along the thrust surface serving and bounding the hinterland-dipping duplex. / M.S.

M.S.

The competitive nature of the modern manufacturing industry coupled with increasing consumer demand and a dynamic economy, lead manufacturers to operate their production computer numerical control (CNC) machines beyond their capable operational limits. This unsustainable behaviour leads to the rapid deterioration and breakdown of the CNC’s critical subsystems and components. Consequently, increasing the amount of unplanned downtime and cost of maintenance. To put it into perspective, downtime in the automotive manufacturing sector can reach upwards of USD 2 million per hour. The linear axis is one of the CNC’s critical subsystems, its robust and accurate positioning capabilities drive the operational and geometric performance of CNC machines. Failure to promptly address developed faults in the linear axis, may lead to poor geometric performance and system sluggishness, overall affecting the production quality of manufactured products. Therefore, it is crucial to monitor the health condition of this subsystem and its components. The principal aim of the presented research was to develop a condition-based monitoring (CBM) system to monitor the health condition of the linear axis and its various components. To achieve this aim, the research work was divided into four objectives. Firstly, objective one consisted of designing an industrial level linear axis testbed that resembles a CNCs linear axis to conduct all experiments. Furthermore, the testbed’s main contribution is to serve as a data generation platform for the research community. Objective two focused in the design of a framework to establish a reference baseline dataset for CBM systems. The framework’s contribution consisted of building an understanding of the healthy condition of the linear axis and its components using vibration monitoring and time domain statistical feature analysis. It was found that under a known healthy condition the time domain features exhibit low variability, there is a negligible difference between a forward and reverse stroke, and a robust baseline can be established by collecting data for approximately an hour of operation rather than a 6-hour operational shift. The third objective of the research consisted in conducting a comprehensive health assessment of the linear axis and its components through a multi-sensor approach, when a root-cause failure fault (FF) is present. Additionally, the health assessment’s contribution was further enhanced by analyzing the repair condition of these faults and comparing the results to the original baseline. The assessment demonstrated that the most frequently occurring root-cause FF, carrier block raceway blockage, can easily be detected through the system’s internal data. Moreover, the repair state condition exhibited less than 10% error when compared to the baseline state. Finally, the fourth objective was centered in the development and application of a novel signal segmentation technique to detect and localize the leading root-cause of failure in the linear axis, misalignment. The technique’s main contribution rests in its functionality as a localization and verification tool in linear axis maintenance. The findings from the conducted studies revealed that the technique increased the usability of time domain features such as RMS, by approximately double. Lastly, the evaluation of both stroke directions aided in localizing the misalignment in the linear axis. / Thesis / Doctor of Philosophy (PhD) / Computer numerical control (CNC) machines are pivotal assets for the manufacturing sector, yet the demand from the modern industry often drives the operation of these machines to exceed their capable operational limits. Consequently, causing the breakdowns of their critical subsystems, resulting in high maintenance costs and machine downtime. The linear axis is one of these critical subsystems, primarily tasked with the positioning function in the CNC machine. In the presented research, a condition-based monitoring (CBM) system was developed, to monitor the health state of this critical subsystem and its components. The development of the system first focused on understanding the healthy condition of a linear axis and its components by implementing a statistics-based baseline dataset framework. Then, a comprehensive health assessment was conducted to evaluate multiple data streams and detect signal variation when root cause failure faults (FFs) are present in the system. Unlike previous health assessments, the repair condition of the evaluated components was also included in the analysis. Finally, a novel signal segmentation algorithm was developed to complement the CBM system, specifically serving as a localization tool to pinpoint an artificially induced misalignment on the guide rail component of the linear axis.

Broken-formations (Hsu, 1974; Harris and Milici, 1977) occur in the lower part of the Pulaski thrust sheet and contain some of the most strongly deformed sedimentary rocks in the Valley and Ridge province of the southern Appalachians. Deformation in this zone ranges from grain-scale cataclasis to regional-scale faulting. The broken-formations are distinguished from rocks structurally higher on the sheet and from rocks of the underlying Saltville sheet by (1) a sharp increase in the variability of fold and fault styles, (2) greater ranges in fold plunges and dips of axial surfaces, (3) a low degree of preferred orientation of folds and faults, (4) an increase in the frequency of mesoscopic structures, and (5) the presence of Max Meadows tectonic breccia. Structural analyses indicate that deformation in the broken-formations is Alleghanian in age and that the deformed zone formed under elastico-frictional conditions, possibly under elevated fluid pressures with temporally variant stresses and that lithology may have played an important role in localizing the broken-formations along the base of the Pulaski sheet. / Ph. D.

Thesis (Ph. D.)--University of Oregon, 2005. / Typescript. Includes vita and abstract. Includes bibliographical references (leaves 173-185). Also available for download via the World Wide Web; free to University of Oregon users.

Thesis (M.S.)--Miami University, Dept. of Geology, 2005. / Title from first page of PDF document. Document formatted into pages; contains [1], iv, 38 p. : ill. Includes bibliographical references (p. 35-38).

Os algoritmos para síntese de circuitos digitais em geral visam a melhoria de uma função de custo composta de quatro critérios: área, desempenho, potência e testabilidade. Normalmente estes algoritmos conseguem uma relação de compromisso para a otimização de dois critérios. Efeitos indesejáveis também podem surgir com a otimização de um destes critérios. Por exemplo, as otimizações de desempenho podem introduzir falhas de colagem não testáveis (redundâncias) em um circuito, reduzindo a sua testabilidade. Muitos algoritmos de síntese lógica exploram propriedades específicas de determinadas funções a serem sintetizadas. Um exemplo de função com propriedades específicas são as funções ditas unate. Um exemplo deste tipo de função é o sinal de carry de um somador completo. Este tipo de função exige cuidados especiais para evitar a introdução de redundâncias. Muitos dos algoritmos para síntese lógica empregam a decomposição de Shannon para melhorar o desempenho de um circuito. A equação geral da decomposição de Shannon é expressa através de uma função binate. As redundâncias sempre serão introduzidas nos circuitos quando uma equação binate é utilizada para representar uma função unate. Diagramas de Decisão Binária (BDDs) são um tipo estruturas de dados muito utilizadas em algoritmos para síntese lógica. A decomposição de Shannon também é utilizada para derivar circuitos a partir de BDDs. Este tipo de estrutura representa uma função lógica, mas não mantém uma representação sem redundâncias da mesma. Infelizmente, os circuitos derivados a partir desta estrutura poderão ser redundantes, principalmente quando a decomposição de Shannon for utilizada. Existem estruturas de dados capazes de representar uma função sem redundâncias. Este é o caso dos VPBDDs , que possuem propriedades especiais que preservam características de testabilidade da função representada. Baseando-se nas propriedades dos VPBDDs, um novo algoritmo para remoção de redundâncias foi proposto. Este algoritmo é capaz de gerar circuitos sem redundâncias, mesmo quando a função, que é representada pelo VPBDD, é unate. Além da geração de circuitos sem redundâncias, o algoritmo garante que o atraso do circuito não aumenta após a remoção de redundâncias. A área dos circuitos resultantes pode aumentar, diminuir ou permanecer a mesma, considerando o número de portas lógicas utilizadas. Todos os resultados obtidos neste trabalho mostram que o algoritmo consegue realizar a remoção de redundâncias, sem prejudicar o atraso do circuito. Além disso, todos os caminhos redundantes do circuito têm seu atraso reduzido, pois com a remoção de redundâncias o número de portas lógicas em série é reduzido. A aplicação deste algoritmo apresenta bons resultados para circuitos aritméticos. Isto se deve principalmente ao fato do carry ser uma função unate, o que pode introduzir redundâncias no circuito se esta propriedade (de ser unate) não for tratada adequadamente. O algoritmo proposto também abre possibilidades para a criação de outras ferramentas de CAD, como por exemplo: uma ferramenta para análise de timing, um gerador de circuitos aritméticos sem redundâncias, ou ainda uma ferramenta para geração de teste, incluindo lista de falhas, vetores de teste e cobertura de falhas. / Algorithms for digital circuit design aim the reduction of a cost function composed of four criteria: area, delay, power and testability. Usually these algorithms are able to obtain a trade-off for the optimization of two of these criteria. Undesired effects may occur due to the optimization of one of the criteria. For instance, delay optimizations may introduce non testable stuck-at faults (redundancies) in a circuit, this way reducing its testability. Several logic synthesis algorithms exploit specific properties of the logic functions to be synthesized. One example of function with specific properties are the socalled unate functions. An example of this kind of function is the carry-out sign in a full adder circuit. This kind of function require special care in order to avoid redundancy introduction. Shannon decomposition [SHA 38] is used in many logic synthesis algorithms for improving circuit performance. The general case of the Shannon decomposition is represented by a binate (not unate) equation. Redundancies are introduced in a circuit when a binate equation is used to express a unate function. Binary Decision Diagrams (BDDs) are a kind of data structures widely used in the field of logic synthesis. Shannon decomposition is also used to derive circuits from BDDs. This data structure is used to represent logic functions, but it is not able to maintain an irredundant representation of any logic function. Unfortunately, circuits derived from BDDs will possibly have redundancies, specially when Shannon decomposition is used. Some data structures are able to represent any logic function in a irredundant form. This is the case of the VPBDDs [REI 95a] [REI 2000], which have special properties that preserve the testability properties of the functions being represented. Based on VPBDD properties, a novel algorithm for redundancy removal was proposed [MAR 2002]. This algorithm is able to generate irredundant circuits even when the function represented by the VPBDD is unate. In addition to the generation of irredundant circuits, the algorithm guarantees that the circuit delay will not be increased by redundancy removal. The final area may be increased, reduced or even remain the same, considering the number of logic gates. The results obtained in this work indicate that the algorithm is able to perform redundancy removal without increasing the circuit delay. Besides, all the redundant paths in the circuit have their delay reduced, as the number of logic gates in series will be reduced by the redundancy removal process. The application of this algorithm gives good results for arithmetic circuits. This is mainly due to the fact that the carry chain is composed of unate functions, this way redundancies are introduced in the circuit if this property is not adequately treated. The proposed algorithm allows for the creation of other CAD tools, as for instance: a timing analysis tool, a generator of irredundant arithmetic circuits, or even a test generation tool, including list of faults, test vectors as well as fault coverage.

Os algoritmos para síntese de circuitos digitais em geral visam a melhoria de uma função de custo composta de quatro critérios: área, desempenho, potência e testabilidade. Normalmente estes algoritmos conseguem uma relação de compromisso para a otimização de dois critérios. Efeitos indesejáveis também podem surgir com a otimização de um destes critérios. Por exemplo, as otimizações de desempenho podem introduzir falhas de colagem não testáveis (redundâncias) em um circuito, reduzindo a sua testabilidade. Muitos algoritmos de síntese lógica exploram propriedades específicas de determinadas funções a serem sintetizadas. Um exemplo de função com propriedades específicas são as funções ditas unate. Um exemplo deste tipo de função é o sinal de carry de um somador completo. Este tipo de função exige cuidados especiais para evitar a introdução de redundâncias. Muitos dos algoritmos para síntese lógica empregam a decomposição de Shannon para melhorar o desempenho de um circuito. A equação geral da decomposição de Shannon é expressa através de uma função binate. As redundâncias sempre serão introduzidas nos circuitos quando uma equação binate é utilizada para representar uma função unate. Diagramas de Decisão Binária (BDDs) são um tipo estruturas de dados muito utilizadas em algoritmos para síntese lógica. A decomposição de Shannon também é utilizada para derivar circuitos a partir de BDDs. Este tipo de estrutura representa uma função lógica, mas não mantém uma representação sem redundâncias da mesma. Infelizmente, os circuitos derivados a partir desta estrutura poderão ser redundantes, principalmente quando a decomposição de Shannon for utilizada. Existem estruturas de dados capazes de representar uma função sem redundâncias. Este é o caso dos VPBDDs , que possuem propriedades especiais que preservam características de testabilidade da função representada. Baseando-se nas propriedades dos VPBDDs, um novo algoritmo para remoção de redundâncias foi proposto. Este algoritmo é capaz de gerar circuitos sem redundâncias, mesmo quando a função, que é representada pelo VPBDD, é unate. Além da geração de circuitos sem redundâncias, o algoritmo garante que o atraso do circuito não aumenta após a remoção de redundâncias. A área dos circuitos resultantes pode aumentar, diminuir ou permanecer a mesma, considerando o número de portas lógicas utilizadas. Todos os resultados obtidos neste trabalho mostram que o algoritmo consegue realizar a remoção de redundâncias, sem prejudicar o atraso do circuito. Além disso, todos os caminhos redundantes do circuito têm seu atraso reduzido, pois com a remoção de redundâncias o número de portas lógicas em série é reduzido. A aplicação deste algoritmo apresenta bons resultados para circuitos aritméticos. Isto se deve principalmente ao fato do carry ser uma função unate, o que pode introduzir redundâncias no circuito se esta propriedade (de ser unate) não for tratada adequadamente. O algoritmo proposto também abre possibilidades para a criação de outras ferramentas de CAD, como por exemplo: uma ferramenta para análise de timing, um gerador de circuitos aritméticos sem redundâncias, ou ainda uma ferramenta para geração de teste, incluindo lista de falhas, vetores de teste e cobertura de falhas. / Algorithms for digital circuit design aim the reduction of a cost function composed of four criteria: area, delay, power and testability. Usually these algorithms are able to obtain a trade-off for the optimization of two of these criteria. Undesired effects may occur due to the optimization of one of the criteria. For instance, delay optimizations may introduce non testable stuck-at faults (redundancies) in a circuit, this way reducing its testability. Several logic synthesis algorithms exploit specific properties of the logic functions to be synthesized. One example of function with specific properties are the socalled unate functions. An example of this kind of function is the carry-out sign in a full adder circuit. This kind of function require special care in order to avoid redundancy introduction. Shannon decomposition [SHA 38] is used in many logic synthesis algorithms for improving circuit performance. The general case of the Shannon decomposition is represented by a binate (not unate) equation. Redundancies are introduced in a circuit when a binate equation is used to express a unate function. Binary Decision Diagrams (BDDs) are a kind of data structures widely used in the field of logic synthesis. Shannon decomposition is also used to derive circuits from BDDs. This data structure is used to represent logic functions, but it is not able to maintain an irredundant representation of any logic function. Unfortunately, circuits derived from BDDs will possibly have redundancies, specially when Shannon decomposition is used. Some data structures are able to represent any logic function in a irredundant form. This is the case of the VPBDDs [REI 95a] [REI 2000], which have special properties that preserve the testability properties of the functions being represented. Based on VPBDD properties, a novel algorithm for redundancy removal was proposed [MAR 2002]. This algorithm is able to generate irredundant circuits even when the function represented by the VPBDD is unate. In addition to the generation of irredundant circuits, the algorithm guarantees that the circuit delay will not be increased by redundancy removal. The final area may be increased, reduced or even remain the same, considering the number of logic gates. The results obtained in this work indicate that the algorithm is able to perform redundancy removal without increasing the circuit delay. Besides, all the redundant paths in the circuit have their delay reduced, as the number of logic gates in series will be reduced by the redundancy removal process. The application of this algorithm gives good results for arithmetic circuits. This is mainly due to the fact that the carry chain is composed of unate functions, this way redundancies are introduced in the circuit if this property is not adequately treated. The proposed algorithm allows for the creation of other CAD tools, as for instance: a timing analysis tool, a generator of irredundant arithmetic circuits, or even a test generation tool, including list of faults, test vectors as well as fault coverage.