Os algoritmos para síntese de circuitos digitais em geral visam a melhoria de uma função de custo composta de quatro critérios: área, desempenho, potência e testabilidade. Normalmente estes algoritmos conseguem uma relação de compromisso para a otimização de dois critérios. Efeitos indesejáveis também podem surgir com a otimização de um destes critérios. Por exemplo, as otimizações de desempenho podem introduzir falhas de colagem não testáveis (redundâncias) em um circuito, reduzindo a sua testabilidade. Muitos algoritmos de síntese lógica exploram propriedades específicas de determinadas funções a serem sintetizadas. Um exemplo de função com propriedades específicas são as funções ditas unate. Um exemplo deste tipo de função é o sinal de carry de um somador completo. Este tipo de função exige cuidados especiais para evitar a introdução de redundâncias. Muitos dos algoritmos para síntese lógica empregam a decomposição de Shannon para melhorar o desempenho de um circuito. A equação geral da decomposição de Shannon é expressa através de uma função binate. As redundâncias sempre serão introduzidas nos circuitos quando uma equação binate é utilizada para representar uma função unate. Diagramas de Decisão Binária (BDDs) são um tipo estruturas de dados muito utilizadas em algoritmos para síntese lógica. A decomposição de Shannon também é utilizada para derivar circuitos a partir de BDDs. Este tipo de estrutura representa uma função lógica, mas não mantém uma representação sem redundâncias da mesma. Infelizmente, os circuitos derivados a partir desta estrutura poderão ser redundantes, principalmente quando a decomposição de Shannon for utilizada. Existem estruturas de dados capazes de representar uma função sem redundâncias. Este é o caso dos VPBDDs , que possuem propriedades especiais que preservam características de testabilidade da função representada. Baseando-se nas propriedades dos VPBDDs, um novo algoritmo para remoção de redundâncias foi proposto. Este algoritmo é capaz de gerar circuitos sem redundâncias, mesmo quando a função, que é representada pelo VPBDD, é unate. Além da geração de circuitos sem redundâncias, o algoritmo garante que o atraso do circuito não aumenta após a remoção de redundâncias. A área dos circuitos resultantes pode aumentar, diminuir ou permanecer a mesma, considerando o número de portas lógicas utilizadas. Todos os resultados obtidos neste trabalho mostram que o algoritmo consegue realizar a remoção de redundâncias, sem prejudicar o atraso do circuito. Além disso, todos os caminhos redundantes do circuito têm seu atraso reduzido, pois com a remoção de redundâncias o número de portas lógicas em série é reduzido. A aplicação deste algoritmo apresenta bons resultados para circuitos aritméticos. Isto se deve principalmente ao fato do carry ser uma função unate, o que pode introduzir redundâncias no circuito se esta propriedade (de ser unate) não for tratada adequadamente. O algoritmo proposto também abre possibilidades para a criação de outras ferramentas de CAD, como por exemplo: uma ferramenta para análise de timing, um gerador de circuitos aritméticos sem redundâncias, ou ainda uma ferramenta para geração de teste, incluindo lista de falhas, vetores de teste e cobertura de falhas. / Algorithms for digital circuit design aim the reduction of a cost function composed of four criteria: area, delay, power and testability. Usually these algorithms are able to obtain a trade-off for the optimization of two of these criteria. Undesired effects may occur due to the optimization of one of the criteria. For instance, delay optimizations may introduce non testable stuck-at faults (redundancies) in a circuit, this way reducing its testability. Several logic synthesis algorithms exploit specific properties of the logic functions to be synthesized. One example of function with specific properties are the socalled unate functions. An example of this kind of function is the carry-out sign in a full adder circuit. This kind of function require special care in order to avoid redundancy introduction. Shannon decomposition [SHA 38] is used in many logic synthesis algorithms for improving circuit performance. The general case of the Shannon decomposition is represented by a binate (not unate) equation. Redundancies are introduced in a circuit when a binate equation is used to express a unate function. Binary Decision Diagrams (BDDs) are a kind of data structures widely used in the field of logic synthesis. Shannon decomposition is also used to derive circuits from BDDs. This data structure is used to represent logic functions, but it is not able to maintain an irredundant representation of any logic function. Unfortunately, circuits derived from BDDs will possibly have redundancies, specially when Shannon decomposition is used. Some data structures are able to represent any logic function in a irredundant form. This is the case of the VPBDDs [REI 95a] [REI 2000], which have special properties that preserve the testability properties of the functions being represented. Based on VPBDD properties, a novel algorithm for redundancy removal was proposed [MAR 2002]. This algorithm is able to generate irredundant circuits even when the function represented by the VPBDD is unate. In addition to the generation of irredundant circuits, the algorithm guarantees that the circuit delay will not be increased by redundancy removal. The final area may be increased, reduced or even remain the same, considering the number of logic gates. The results obtained in this work indicate that the algorithm is able to perform redundancy removal without increasing the circuit delay. Besides, all the redundant paths in the circuit have their delay reduced, as the number of logic gates in series will be reduced by the redundancy removal process. The application of this algorithm gives good results for arithmetic circuits. This is mainly due to the fact that the carry chain is composed of unate functions, this way redundancies are introduced in the circuit if this property is not adequately treated. The proposed algorithm allows for the creation of other CAD tools, as for instance: a timing analysis tool, a generator of irredundant arithmetic circuits, or even a test generation tool, including list of faults, test vectors as well as fault coverage.

<div> <div> <div> <p>Various fault models such as stuck-at, transition, bridging have been developed to better model possible defects in manufactured chips. However, over the years as device sizes have shrunk, the probability of systematic defects occurring in chips has increased. To predict the sites of occurrence of such defects, Design-for-Manufacturability (DFM) guidelines have been established, the violations of which are modelled into DFM faults. Nonetheless, some faults corresponding to DFM as well as other fault models are undetectable, i.e., tests cannot be generated to detect their presence. It has been seen that undetectable faults usually tend to cluster together, leaving large areas in a circuit uncovered. As a result, defects occurring there, even if detectable, go undetected because there are no tests covering those areas. Hence, this becomes an important issue to address, and to resolve it, we utilize gate- exhaustive faults to cover these areas. Gate-exhaustive faults provide exhaustive coverage to gates. They can detect any defect which is not modelled by any other fault model. However, the total number of gate-exhaustive faults in a circuit can be quite large and may require many test patterns for detection. Therefore, we use procedures to select only those faults which can provide additional coverage to the sites of undetectable faults. We de ne parameters that determine whether a gate associated with one or more undetectable faults is covered or not, depending on the number of detectable and useful gate-exhaustive faults present around the gate. Bridging faults are also added for extra coverage. These procedures applied to benchmark circuits are used for obtaining the experimental results. The results show that the sizes of clusters of undetectable faults are reduced, upon the addition of gate-exhaustive faults to the fault set, both in the case of single-cycle and two-cycle faults. </p> </div> </div> </div>

The state gravity maps of Oregon and Washington show a gravity high centered south of Portland, Oregon and a gravity low in the Tualatin Valley to the west disrupting the regional gravity gradient which is controlled by crustal thickening. Detailed gravity surveys done in the Portland area are consistent with the state gravity maps but show considerably more detail. Quantitative interpretation of this data has provided new information on the subsurface structure in this area; recent work has yielded corroborative evidence for a fault zone bounding the east side of the Portland Hills, and has indicated the presence of faults under the Portland Basin to the east which were previously unknown.

The Fries Fault, a 1.2-2.3 km wide zone near Riner, is a major tectonic discontinuity in the Blue Ridge geologic province, characterized by progressive stages of continuous ductile deformation. Trending northeast with a shallow to moderate southeast dip, this fault juxtaposes Little River Gneiss on the southeast against Pilot Gneiss and the Chilhowee Formation to the northwest. A 0.8-1.2 km wide subzone of protomylonite within the Little River Gneiss grades into a 0.5-1.0 km wide mylonite subzone, the latter containing narrow bands of phyllotactic ultramylonite ranging in width from centimeters to tens of meters. Mylonitization is reflected by a marked reduction in grain size, elongation of quartz and fracturing of feldspar, all concomitant with the development of a mylonitic foliation (S_m). Ductile deformation processes involving grain elongation, recovery and recrystallization, combined with chemical processes (primarily pressure solution), are the dominant strain-accommodation mechanisms in the formation of S_m. Rocks within the fault zone have undergone four phases of Paleozoic deformation. An early S₁ foliation has been nearly completely transposed by S_m(S₂), which dominates across most of the area. The development of S_m was accompanied by a retrogressive metamorphism that altered basement rocks from lower amphibolite to greenschist facies. Chilhowee Group rocks remained at lower greenschist facies. Post-faulting deformation produced an S₃ crenulation cleavage associated with northeast trending, overturned F₃ folds. Subsequent refolding produced open, northwest trending F₄ folds. Although the bulk deformation is progressive simple shear, flattening is increasingly dominant during the later stages of deformation. / Master of Science

Os motores de indução desempenham um importante papel na indústria, fato este que destaca a importância do correto diagnóstico e classificação de falhas ainda em fase inicial de sua evolução, possibilitando aumento na produtividade e, principalmente, eliminando graves danos aos processos e às máquinas. Assim, a proposta desta tese consiste em apresentar um multiclassificador inteligente para o diagnóstico de motor sem defeitos, falhas de curto-circuito nos enrolamentos do estator, falhas de rotor e falhas de rolamentos em motores de indução trifásicos acionados por diferentes modelos de inversores de frequência por meio da análise das amplitudes dos sinais de corrente de estator no domínio do tempo. Para avaliar a precisão de classificação frente aos diversos níveis de severidade das falhas, foram comparados os desempenhos de quatro técnicas distintas de aprendizado de máquina; a saber: (i) Rede Fuzzy Artmap, (ii) Rede Perceptron Multicamadas, (iii) Máquina de Vetores de Suporte e (iv) k-Vizinhos-Próximos. Resultados experimentais obtidos a partir de 13.574 ensaios experimentais são apresentados para validar o estudo considerando uma ampla faixa de frequências de operação, bem como regimes de conjugado de carga em 5 motores diferentes. / Induction motors play an important role in the industry, a fact that highlights the importance of correct diagnosis and classification of faults on these machines still in early stages of their evolution, allowing increase in productivity and mainly, eliminating major damage to the processes and machines. Thus, the purpose of this thesis is to present an intelligent multi-classifier for the diagnoses of healthy motor, short-circuit faults in the stator windings, rotor broken bars and bearing faults in induction motors operating with different models of frequency inverters by analyzing the amplitude of the stator current signal in the time domain. To assess the classification accuracy across the various levels of faults severity, the performances of four different learning machine techniques were compared; namely: (i) Fuzzy ARTMAP network, (ii) Multilayer Perceptron Network, (iii) Support Vector Machine and (iv) k-Nearest-Neighbor. Experimental results obtained from 13.574 experimental tests are presented to validate the study considering a wide range of operating frequencies and also load conditions using 5 different motors.

Os motores de indução desempenham um importante papel na indústria, fato este que destaca a importância do correto diagnóstico e classificação de falhas ainda em fase inicial de sua evolução, possibilitando aumento na produtividade e, principalmente, eliminando graves danos aos processos e às máquinas. Assim, a proposta desta tese consiste em apresentar um multiclassificador inteligente para o diagnóstico de motor sem defeitos, falhas de curto-circuito nos enrolamentos do estator, falhas de rotor e falhas de rolamentos em motores de indução trifásicos acionados por diferentes modelos de inversores de frequência por meio da análise das amplitudes dos sinais de corrente de estator no domínio do tempo. Para avaliar a precisão de classificação frente aos diversos níveis de severidade das falhas, foram comparados os desempenhos de quatro técnicas distintas de aprendizado de máquina; a saber: (i) Rede Fuzzy Artmap, (ii) Rede Perceptron Multicamadas, (iii) Máquina de Vetores de Suporte e (iv) k-Vizinhos-Próximos. Resultados experimentais obtidos a partir de 13.574 ensaios experimentais são apresentados para validar o estudo considerando uma ampla faixa de frequências de operação, bem como regimes de conjugado de carga em 5 motores diferentes. / Induction motors play an important role in the industry, a fact that highlights the importance of correct diagnosis and classification of faults on these machines still in early stages of their evolution, allowing increase in productivity and mainly, eliminating major damage to the processes and machines. Thus, the purpose of this thesis is to present an intelligent multi-classifier for the diagnoses of healthy motor, short-circuit faults in the stator windings, rotor broken bars and bearing faults in induction motors operating with different models of frequency inverters by analyzing the amplitude of the stator current signal in the time domain. To assess the classification accuracy across the various levels of faults severity, the performances of four different learning machine techniques were compared; namely: (i) Fuzzy ARTMAP network, (ii) Multilayer Perceptron Network, (iii) Support Vector Machine and (iv) k-Nearest-Neighbor. Experimental results obtained from 13.574 experimental tests are presented to validate the study considering a wide range of operating frequencies and also load conditions using 5 different motors.

<p> <p>&nbsp / </p> </p> <p align="left">The underlying theme of this thesis is identification, classification, detection and prediction of cellular network faults using state of the art technologies, methods and algorithms.</p>

The Valle de Catacamas forms a major basin along the central portion of the Guayape fault, the most prominent tectonic element of the Chortís block. The Guayape fault extends 290 km southwest from the Caribbean coast to the region of El Paraíso, Honduras, and may continue to the Pacific coast along a related prominent topographic feature, the Choluteca linear. Basins presently forming along the Guayape fault indicate that the fault is currently experiencing right-slip. The active features of the Valle de Catacamas displace older folds and reverse faults which apparently formed during an earlier period of sinistral shear. Thus, the Guayape fault has undergone at least two phases of movement, post-Cenomanian left-slip followed by the present right-slip. The geology of the valley suggests multiple stages of evolution. These include at least one period of thrust and reverse faulting, possibly associated with sinistral shear along the Guayape fault, and a recent episode of normal faulting associated with dextral shear on the Guayape fault. Thrusting of basement rocks over Jurassic strata on the south side of the valley was the earliest deformation to affect Mesozoic or Cenozoic rocks. The event can only be dated as post-Jurassic in age. The Cretaceous rocks of the Sierra de Agalta on the north side of the Valle de Catacamas are much more strongly deformed than similar rocks in central Honduras. In this range, the Aptian-Albian Atima Limestone commonly has a pervasive pressure solution cleavage which has not been reported from other locations on the Chortís block. The cleavage is apparently axial planar to the folds. The age of this deformation is constrained only as post-Cenomanian. SIR data indicate that these folds are deflected in sinistral shear near the Guayape fault. In addition, a major structural contact has a large left-lateral separation. The folds in the Sierra de Agalta are cut by the range-bounding normal fault of the Sierra de Agalta. Younger rocks are placed on older rocks by this normal fault, and fault slip data from small fault planes in the footwall block indicate normal faulting. The N 65° E strike of this normal fault, the N 35° E strike of the Guayape fault, and stress orientations inferred from fault slip data indicate that the present movement on the Guayape fault is right-slip. Fault slip data from the Guayape fault zone is heterogeneous as would be expected if two stage slip has occurred. / text

<p> <p>&nbsp / </p> </p> <p align="left">The underlying theme of this thesis is identification, classification, detection and prediction of cellular network faults using state of the art technologies, methods and algorithms.</p>

Philosophiae Doctor - PhD / The underlying theme of this thesis is identification, classification, detection and prediction of cellular network faults using state of the art technologies, methods and algorithms.