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Multiple dielectric crossing waveguides are indispensable in building a complex optical integrated circuit. Since each input/output waveguide will have many crossings, it is important to design a low-loss waveguide crossing to ensure the overall radiation loss is kept at a minimum. The beam propagation method (BPM) is usually the method of choice for modeling large but low-index-contrast waveguide devices. BPM assumes one-way propagation and adopts the paraxial approximation. It is neither able to consider reflection of electromagnetic (EM) fields nor to perform wide angle propagation of forward fields. Therefore, it can not be used to analyze perpendicular dielectric crossing waveguides. At a maximum 0.5 dB power loss per crossing, the difficulty of simulation a waveguide crossing is how to compute the complex coupling waves with high enough precision. In this thesis, two-dimensional planar integrated optical waveguide crossing is studied in detail for the through and cross power coupling coefficients with the finite-difference frequency-domain (FD-FD) method. By exploiting the dual symmetries: the ¡§+¡¨ symmetry and the ¡§X¡¨ symmetry in the perpendicular crossing waveguide, we are able to compute the EM fields and their power coefficients without using artificial absorbing boundary conditions (ABC) nor using the perfectly matching layer (PML). We develop the layer-mode based transparent boundary condition (LM-TBC) [1] for launching the fundamental incident mode as well as transmitting the reflected and scattered wave fields off the crossing area. Numerical results including the field distribution, power coefficients are carefully verified and the convergent comparisons are also studied in the thesis.

Realistic predictions of service life of steel catenary risers (SCR) require an accurate characterization of seafloor stiffness in the region where the riser contacts the seafloor, the so-called touchdown zone. This thesis presents the initial stage of development of a simplified seafloor support model. This model simulates the seafloor-pipe interaction as a flexible pipe supported on a bed of springs. Constants for the soil springs were derived from finite element studies performed in a separate, parallel investigation. These supports are comprised of elasto-plastic springs with spring constants being a function of soil stiffness and strength, and the geometry of the trench within the touchdown zone. Deflections and bending stresses in the pipe are computed based on a finite element method and a finite difference formulation developed in this research project. The finite difference algorithm has capabilities for analyzing linear springs, non-linear springs, and springs having a tension cut-off. The latter feature simulates the effect of a pipe pulling out of contact with the soil. The model is used to perform parametric studies to assess the effects of soil stiffness, soil strength, trench geometry, amplitude of pipe displacements, pipe stiffness, and length of touchdown zone on pipe deflections and bending stresses. In conclusions, the seafloor stiffness (as characterized by the three spring parameters), the magnitude of pipe displacement, and the length of the touchdown zone all influence bending stresses in the pipe. Also, the tension cutoff effect, i.e., the pipe pulling away from the soil, can have a very large effect on bending stresses in the pipe. Neglecting this effect can lead to serious over-estimate of stress levels and excessive conservatism in design.

Realistic predictions of service life of steel catenary risers (SCR) require an accurate characterization of seafloor stiffness in the region where the riser contacts the seafloor, the so-called touchdown zone. This thesis presents the initial stage of development of a simplified seafloor support model. This model simulates the seafloor-pipe interaction as a flexible pipe supported on a bed of springs. Constants for the soil springs were derived from finite element studies performed in a separate, parallel investigation. These supports are comprised of elasto-plastic springs with spring constants being a function of soil stiffness and strength, and the geometry of the trench within the touchdown zone. Deflections and bending stresses in the pipe are computed based on a finite element method and a finite difference formulation developed in this research project. The finite difference algorithm has capabilities for analyzing linear springs, non-linear springs, and springs having a tension cut-off. The latter feature simulates the effect of a pipe pulling out of contact with the soil. The model is used to perform parametric studies to assess the effects of soil stiffness, soil strength, trench geometry, amplitude of pipe displacements, pipe stiffness, and length of touchdown zone on pipe deflections and bending stresses. In conclusions, the seafloor stiffness (as characterized by the three spring parameters), the magnitude of pipe displacement, and the length of the touchdown zone all influence bending stresses in the pipe. Also, the tension cutoff effect, i.e., the pipe pulling away from the soil, can have a very large effect on bending stresses in the pipe. Neglecting this effect can lead to serious over-estimate of stress levels and excessive conservatism in design.

Univ., Diss., 2009--Bayreuth.

No description available.

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Devido à sua alta taxa de mortalidade as doenças cardiovasculares vem sendo foco de pesquisas nos últimos anos. Estima-se que neste grupo, 42% das mortes foram consequência de doença coronariana (CHD) em 2012. Para auxiliar o acompanhamento de pacientes com CHD, este estudo teve como objetivo investigar um método simples e robusto que segmenta de maneira semi-automática a área da neoíntima em Tomografias Intravasculares por Coerência Óptica no Domínio da Frequência (FD-IOCT), a mais recente técnica de imagear vasos internamente. O método foi dividido em duas etapas. A primeira segmenta a área contida pelo lúmen através de operações morfológicas com valores de intensidade e aplicação da limiarização Otsu. Na segunda, o foco foi segmentar a área contida por partes de stent onde duas estratégias foram desenvolvidas e comparadas. Ambas as etapas (segmentação de área de lúmen e de stent) obtiveram resultados acurados com aproximadamente 98% de Verdadeiro Positivo, enquanto o Falso Positivo foi próximo de 3% para o lúmen e 5% para stent, onde uma das estratégias (para delimitar a área contida por stent) apresentou um tempo de execução 50 vezes maior que a outra. O método foi utilizado em 443 imagens com diferentes características e os resultados são encorajadores. / Due to its high mortality rate cardiovascular diseases have been the focus of research in recent years. It is estimated that among these, 42% of deaths were due to coronary heart disease (CHD) in 2012. To monitor patients with CHD, the goal of this study was to investigate a simple and robust method that segments semi-automatically the neointimal area on Frequency Domain Intravascular Optical Coherence Tomography (FD-IOCT), the latest technology to view vessels internally. The method was divided into two steps. The first one segments the area contained by the lumen through morphological operations on intensity values and the Otsu threshold. In the second one, the focus was to segment the area contained by stent struts where two strategies were developed and compared. Both steps (lumen and stent strut area segmentation) obtained accurate results with true positives approximately 98%, while the false positives were close to 3% for the lumen and 5% for the stent, where one strategy (to delimit the area contained by stent struts) showed run time of 50 times the other. The method was executed on 443 images with different characteristics and the results are encouraging.

Aujourd'hui, il existe plusieurs façons de développer des circuits microélectroniques adaptés aux applications spatiales qui répondent aux contraintes sévères de l'immunité contre les radiations, que ce soit en termes de technique de conception ou de processus de fabrication. Le but de ce doctorat est d'une part de combiner plusieurs techniques nouvelles de microélectronique pour concevoir des architectures adaptées à ce type d'application et d'autre part, d'incorporer des composants magnétiques non-volatiles intrinsèquement robustes aux rayonnements. Un tel couplage serait tout à fait novateur et profiterait sans précédent, en termes de surface, de consommation, de robustesse et de coût.Contrairement à la conception de circuits synchrones qui reposent sur un signal d'horloge, les circuits asynchrones ont l'avantage d'être plus ou moins insensibles aux variations temporel résultant par exemple des variations du processus de fabrication. En outre, en évitant l'utilisation d'une horloge, les circuits asynchrones ont une consommation d'énergie relativement faible. Les circuits asynchrones sont généralement conçus pour fonctionner en fonction des événements déterminés grâce à un protocole de "poignée de main" spécifique.Pour les applications avioniques et spatiales, il serait souhaitable de fournir un circuit asynchrone rendu robuste contre les effets des radiations. En effet, la présence de particules ionisantes à haute altitude ou dans l'espace peut induire des courants perturbateurs dans des circuits intégrés qui peuvent être suffisants pour provoquer un basculement à l'état binaire maintenu par une ou plusieurs grilles. Cela peut provoquer un dysfonctionnement du circuit, connu dans l'état de l'art en tant que single event upset (SEU). Il a été proposé de fournir un module redondant double (Dual Modular Redundency: DMR) ou un module redondant triple (Tripple Modular Redundcy: TMR) dans une conception de circuit asynchrone afin de fournir une protection contre les radiations. De telles techniques s'appuient sur la duplication du circuit dans le cas de DMR, ou en triplant le circuit dans le cas de TMR, et en détectant une discordance entre les sorties des circuits comme indication de l'apparition d'une SEU.L'intégration de composants non-volatils intrinsèquement robustes, tels que les jonctions de tunnel magnétique (JTM), l'élément principal de la mémoire MRAM, pourrait conduire à de nouvelles façons de retenir les données dans des environnements difficiles. Les dispositifs JTM sont constitués de matériaux ferromagnétiques avec des propriétés magnétiques qui ne sont pas sensibles aux rayonnements. Les données sont stockées sous la forme de la direction de l'aimantation et non sous la forme d'une charge électrique, qui est une propriété essentielle pour les applications spatiales. Il est également largement reconnu dans le domaine de la microélectronique que les circuits intégrés fabriqués sur les substrats SOI (Silicon On Insulator) sont plus robustes aux radiations.Il existe donc un besoin dans l'état de l'art pour un circuit ayant une surface et une consommation d'énergie relativement faibles, et qui permet une récupération après un SEU sans nécessiter de réinitialisation et qui présente des caractéristiques non-volatiles. L'objectif de ce doctorat est de combiner tous les avantages mentionnés ci-dessus en regroupant plusieurs méthodes de conception microélectronique répondant aux contraintes des applications spatiales dans une nouvelle architecture. Un Circuit complet a été imaginé, conçu, simulé et envoyé en fabrication. Ce circuit est composé d'un pipeline asynchrone d'additionneur et d'un test intégré complexe connu sous le nom de BIST (Built In Self Test). Apres fabrication, ce circuit sera testé. Premièrement des tests fonctionnels vont être réalisés, puis des tests sous laser pulsé seront menés ainsi que sous attaques aux ions lourds. / Today, there are several ways to develop microelectronic circuits adapted for space applications that meet the harsh constraints of immunity towards radiation, whether in terms of technical design or manufacturing process. The aim of this doctorate is on the one hand to combine several novel techniques of microelectronics to design architectures adapted to this type of application, and on the other hand to incorporate non-volatile magnetic components inherently robust to radiation. Such an assembly would be quite innovative and would benefit without precedent, in terms of surface, consumption, robustness and cost.In contrast with synchronous circuit designs that rely on a clock signal, asynchronous circuits have the advantage of being more or less insensitive to delay variations resulting for example from variations in the manufacturing process. Furthermore, by avoiding the use of a clock, asynchronous circuits have relatively low power consumption. Asynchronous circuits are generally designed to operate based on events determined using a specific handshake protocol.For aviation and/or spatial applications, it would be desirable to provide an asynchronous circuit that is rendered robust against the effects of radiation. Indeed, the presence of ionising particles at high altitudes or in space can induce currents in integrated circuits that may be enough to cause a flip in the binary state held by one or more gates. This may cause the circuit to malfunction, known in the art as a single event upset (SEU). It has been proposed to provide dual modular redundancy (DMR) or triple modular redundancy (TMR) in an asynchronous circuit design in order to provide radiation protection. Such techniques rely on duplicating the circuit in the case of DMR, or triplicating the circuit in the case of TMR, and detecting a discordance between the outputs of the circuits as an indication of the occurrence of an SEU.The integration of inherently robust non-volatile components, such as Magnetic Tunnel Junctions (MTJ), the main element of MRAM memory, could lead to new ways of data retention in harsh environments. MTJ devices are constituted of ferromagnetic materials with magnetic properties that are not sensitive to radiation. Data is stored in the form of the direction of the magnetisation and not in the form of an electric charge, which is an essential property for space applications. It is also widely recognised in the field of microelectronics that integrated circuits manufactured on SOI (Silicon On Insulator) substrates are more robust to radiation.There is thus a need in the art for a circuit having relatively low surface area and power consumption, and that allows recovery following an SEU without requiring a reset and that has non-volatile characteristics. The objective of this doctorate is to combine all the above mentioned benefits by regrouping several methods of microelectronic design responding to the constraints of space applications into a novel architecture. A complete circuit has been created, designed, simulated, validated and sent to manufacturing in a 28nm FD-SOI process. This circuit is composed of an adder pipeline and a complex BIST (Build In Self Test). When fabricated, this circuit will be tested. First a functional test will be realised, then laser pules attacks will be performed and finally a heavy ions attack campaign.

Deux innovations en matière de procédés technologiques des semi-conducteurs sont des alternatives à la technologie traditionnelle des transistors MOS (« Metal-Oxide-Semiconductor ») « Bulk » planaires : d’une part le silicium totalement déserté sur isolant (FDSOI – « Fully Depleted Silicon on Insulator ») et d’autre part les transistors à effet de champ à aileron (FinFET – « Fin Field Effect Transistor »). En effet, alors que la technologie « Bulk » arrive à ses limites de miniaturisation des composants et systèmes, notamment du fait de l’effet de canal court, ces deux technologies présentent des propriétés prometteuses pour poursuivre cette réduction des dimensions, grâce à un meilleur contrôle électrostatique de la grille sur le canal du transistor. La technologie FDSOI est, comme l’historique « Bulk », une technologie MOS planaire, ce qui la place naturellement davantage dans la continuité technologique que les ailerons verticaux des transistors FinFETs. La compétition entre ces deux technologies est rude et de nombreuses études publiées dans la littérature comparent ces technologies en termes de performance en vitesse de fonctionnement, de consommation, de coût, etc. Néanmoins, aucune étude ne s’était encore penchée sur leurs propriétés respectives en termes de testabilité ; pourtant l’impact de défauts sur les circuits réalisés en technologies FDSOI et FinFET est susceptible d’être significativement de celui induit par des défauts similaires sur des circuits planaires MOS.Le travail présenté dans cette thèse se concentre sur la conception de circuits d’étude similaires dans chacune des trois technologies et l’analyse comparative de leur comportement électrique sous l’effet d’un même défaut. Les défauts considérés dans notre étude sont les courts-circuits résistifs inter-portes, court-circuit résistif à la masse (GND), court-circuit résistif à l’alimentation (VDD), et circuits ouverts résistifs. La détectabilité des défauts est évaluée pour le test logique statique et le test dynamique en « délai ». Des simulations HSPICE et Cadence SPECTRE ont été effectuées en faisant varier la valeur de la résistance du défaut et le concept de résistance critique est utilisé afin de comparer la plage de détectabilité du défaut dans les différentes technologies. Les conditions optimales de polarisation du substrat (« body-biasing »), de tension d’alimentation et de température en vue d’obtenir la meilleure couverture de défauts possible sont déterminées pour chaque type de défaut. Un modèle analytique, basé sur la résistance équivalente des réseaux de transistors N et P actifs (« ON-resistance »), est proposé pour les courts-circuits résistifs, et permet d’évaluer la valeur de la résistance critique sans effectuer de simulation de fautes. Les propriétés en termes de testabilité sont également établies en tenant compte des variations de procédés, par des simulations Monte-Carlo réalisées aussi bien pour les dispositifs à tension de seuil nominale (« Regular-VT devices » : FDSOI-RVT et Bulk-LR) que pour les dispositifs à tension de seuil basse (« Low-VT devices » : FDSOI-LVT et Bulk-LL) disponibles pour les technologies 28 nm Bulk et FDSOI. / Fully Depleted Silicon on Insulator (FDSOI) and Fin Field Effect Transistor (FinFET) are new innovations in silicon process technologies that are likely alternatives to traditional planar Bulk transistors due to their respective promising ways of tackling the scalability issues with better short channel characteristics. Both these technologies are aiming in particular at regaining a better electrostatic control by the gate over the channel of the transistor. FDSOI is a planar MOS technology and as a result it is much more in continuity with planar Bulk as compared to the vertical FinFET transistors. The competition between these two technologies is fierce and many studies have been reported in the literature to compare these technologies in terms of speed performance, power consumption, cost, etc. However, these studies have not yet focused on their testability properties while the impact of defects on circuits implemented in FDSOI and FinFET technologies might be significantly different from the impact of similar defects in planar MOS circuit.The work of this thesis is focused on implementing similar design in each technology and comparing the electrical behavior of the circuit with the same defect. The defects that are considered for our investigation are inter-gate resistive bridging, resistive short to ground terminal (GND), resistive short to power supply (VDD) and resistive open defects. Defect detectability is evaluated in the context of either logic or delay based test. HSPICE and Cadence SPECTRE simulations are performed varying the value of the defect resistance and the concept of critical resistance is used to compare the defect detectability range in different technologies. The optimal body-biasing, supply voltage and temperature settings to achieve the maximum defect coverage are determined for these defect types. An analytical analysis is proposed for short defects based on the ON-resistance of P and N networks, which permits to evaluate the value of the critical resistance without performing fault simulations. Testability properties are also established under the presence of process variations based on Monte-Carlo simulations for both Regular-VT devices (FDSOI-RVT and Bulk-LR) and Low-VT devices (FDSOI-LVT and Bulk-LL) available for 28nm Bulk and FDSOI technologies.