Multimedia applications such as video streaming and Voice over IP are becoming common today with the tremendous growth of the Internet. General purpose operating systems thus are required to support these applications. These multimedia applications have some timing constraints that need to be satisfied for good quality. For example, video streaming applications require that each video frame be decoded in time to be displayed every 33.3 milliseconds. In order to satisfy these timing requirements, general purpose operating systems need to have fine-grained scheduling. Current general purpose operating systems unfortunately are designed to maximize throughput to serve traditional data-oriented applications and have coarse-grained scheduling and timers. Time Sensitive Linux (TSL), designed by Goel, et al., solves this problem with fine-grained timers and schedulers. The scheduler for TSL is implemented at a very low level. The controller that implements the algorithm for resource allocation is implemented at a higher level. This controller can easily be modified to implement new control algorithms. Successful implementation of resource allocation to satisfy timing constraints of multimedia applications requires two problems to be addressed. First, the resources required by the application to satisfy the timing constraints should not exceed the total available resources in the system. Second, the controller must adapt to changing needs of the applications and allocate enough resources to satisfy the timing constraints of each application over time. The first problem has been addressed elsewhere using intelligent data dropping with TSL. We focus on the second problem in this thesis. We design a proportion-period controller in this thesis for allocating CPU to multimedia video applications with timing constraints. The challenges for the controller design include the coarse granularity of the time-stamp markings of the video frames, the unpredictable decoding completion times of the frames, the large variations in the decoding times of the frames, and the limit of the control actuation to positive values. We set up the problem in a state space. We design a predictive estimating controller to allocate the proportion of the CPU to a thread when its long term error is small. When the decoding process is running behind by more than a certain threshold, we switch to a different controller to drive the error back to a small value. This controller is the solution to a dynamic optimization LQR tracking problem. / Graduation date: 2003

Multi-level decision feedback equalization (MDFE) is an effective sampled signal processing technique to remove inter-symbol interference (ISI) from disk read-back signals. Parallelism which doubles the symbol rate can be realized by utilizing the characteristic of channel response and decision feedback equalization algorithm. A mixed-signal IC implementation has been chosen for the parallel MDFE. The differential current signals from the feedback equalizer are subtracted from the forward equalizer output at the summing node to cancel the non-causal ISI. A high-speed comparator with 6 bit resolution is used after the cancellation to detect the signal which contains no ISI. In this thesis, a description of the parallel MDFE structure and decision feedback equalization algorithm are presented. The design of a high-speed summing circuitry and a high-speed comparator are discussed. The same comparator design is used for the flash analog-to-digital converter (ADC) which generates error signals for adaptation.The circuits design and layout were carried out in an HP 1.2-��m n-well CMOS process. / Graduation date: 1998

Reprinted from IEEE transactions on information theory, vol. IT-13, no.3, July 1967. / Bibliography: p. 501.

No description available.

Franklin H. Moss and Adrian Segall. / Bibliography: p. 72. / "September 1978." / Supported by the Advanced Research Project Agency (monitored by ONR) under Contract no. N00014-75-C-1183 Technion Research and Development Foundation Ltd. no. 050-383

Paul K. Houpt ... [et al.]. / Bibliography: leaf [5]. / Caption title. "April, 1980." / Supported in part by NASA under Grant NGL-22-009-124 Advanced Research Projects Agency under Contract N00014-75-C-0061

Thesis (Ph. D.)--Ohio State University, 2006. / Title from first page of PDF file. Includes bibliographical references (p. 88-93).

Critical steps in the design process is the gathering of data, processing the data into a useful form of information (a design concept) which meets specific needs, passing this refined design solution down the path to production, where it is released into the larger environment. With in the designing process there are multiple feedback loops as the solution becomes more refined. Even as it reaches the final end user, other design refinement feedback loops continue as new and improved products or systems. Along with the interdisciplinary teams involved with the product/system development, the more complexity the product or system becomes the more critical the organization of the data becomes. This paper will present and test a concept of a design feedback and feed forward communication tool for product/system design that uses Dr. Walter A. Schaer s Three Functions of an Artifact as the methodological structure for design development. The essence of this design tool is the merging of a new communication system within an existing methodology of organizing complex systems into a morphological matrix, developed by Dr. Walter A. Schaer, based on the Charles Morris s work on semiotics. This communication tool is a new feedback / feed forward mechanism which correspond with the semiotic structure in a morphological matrix to assist the designer develop design solutions. The research will measure the success rate of the tool in the design process, examine of how the designers took advantage of the new tool, and evaluate their perception of its usefulness.

In this work, a 3.5 GHz RF Transmitter and Successive Approximation ADC design has been presented. The transmitter serves as an intermediate block which translates 350 MHz signal into 3.5 GHz signal. This signal is applied to 6-40 GHz wideband transmitter. The emphasis is on the design of Up conversion Mixer with high linearity, low noise and moderate image rejection performance. The successive approximation analog to digital converter was designed as a part of feedback loop control, which consists of a sensor circuit to detect the temperature changes in a power amplifier and the ADC to convert the sensor output to digital data. The data is used to determine the necessary control signals to restore the performance of the power amplifier. The circuits have been designed and implemented in ST Microelectronics CMOS 90nm process.

Thesis (Ph. D.)--University of Missouri-Columbia, 1999. / Typescript. Vita. Includes bibliographical references (leaves 154-159). Also available on the Internet.