Copper interconnects and low k dielectrics have been introduced in advanced IC technology to reduce the interconnect resistance, improve the resistance to electromigration and reduce RC delay and cross talk effects. The introduction of new materials in integrated circuits makes the root cause determination and correction action implementation more challenging. Moreover, the complexity of package structure generates additional impact on degrading the yield of assembly processing manufacture. This main purpose of this study is to investigate the influence of introducing Cu-/Low K wafer phase on actual manufacturing situation. Issues related to the failures of assembly process were analyzed for determining the root cause, in which such as die chipping issue during die sawing process, bond pad peeling/crater issues during wire bonding process and die crack / delamination issues after pre-condition and reliability test. The DOE/JMP methodology was used to achieve the optimium assembly processing condition so as to improve the quality of products, and then the mass production with stable yield could be realized.

This thesis presents a new simulation model for floating gate transistor (FGMOS) in nanometer scale technology where the transistors suffer from non-negligible gate leakage current due to the very thin Silicon oxide (SiO2) layer. The new FGMOS simulation model is used for transient and DC simulation and with any industry standard simulators such as Spector and various SPICE programs (i.e. HSPICE, WinSPICE, etc.). This model can be used for any technology that has SiO2 thickness less than 3nm and suffer from gate leakage current with no changes to the model itself; however, minimal changes need to be done to the gate tunnelling cell to comply with the technology parameters where the gate tunnelling current exponentially increases as tox decreases.

<p>The analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. In these days an ADC becomes a part of the system on chip instead of standalone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, resolution, noise etc. New techniques and methods are going to develop day by day to achieve high performance ADCs.</p><p>Of all types of ADCs the flash ADC is not only famous for its data conversion rate but also it becomes the part of other types of ADC for example pipeline and multi bit Sigma Delta ADCs. The main problem with a flash ADC is its power consumption, which increases in number of bits. This thesis presents the comparison of power consumption of different blocks in 1Gbps flash ADCs for 2, 4 and 6 bits in a 90nm CMOS technology. We also investigate the impact on power consumption by changing the design of decoder block.</p>

The analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. In these days an ADC becomes a part of the system on chip instead of standalone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, resolution, noise etc. New techniques and methods are going to develop day by day to achieve high performance ADCs. Of all types of ADCs the flash ADC is not only famous for its data conversion rate but also it becomes the part of other types of ADC for example pipeline and multi bit Sigma Delta ADCs. The main problem with a flash ADC is its power consumption, which increases in number of bits. This thesis presents the comparison of power consumption of different blocks in 1Gbps flash ADCs for 2, 4 and 6 bits in a 90nm CMOS technology. We also investigate the impact on power consumption by changing the design of decoder block.

In this work, a 3.5 GHz RF Transmitter and Successive Approximation ADC design has been presented. The transmitter serves as an intermediate block which translates 350 MHz signal into 3.5 GHz signal. This signal is applied to 6-40 GHz wideband transmitter. The emphasis is on the design of Up conversion Mixer with high linearity, low noise and moderate image rejection performance. The successive approximation analog to digital converter was designed as a part of feedback loop control, which consists of a sensor circuit to detect the temperature changes in a power amplifier and the ADC to convert the sensor output to digital data. The data is used to determine the necessary control signals to restore the performance of the power amplifier. The circuits have been designed and implemented in ST Microelectronics CMOS 90nm process.

L'activité de recherche scientifique effectuée dans le cadre de mon doctorat de sciences s'est déroulée dans le secteur de la conception de circuits intégrés radiofréquences pour des systèmes ultra-wideband (UWB) et aux ondes millimétriques, et s'est articulée comme suit: (i) circuits intégrés radiofréquences pour émetteur-récepteurbasse puissance pour réseaux locaux wireless; (ii) radar UWB complètement intégré pour la surveillance cardio-pulmonaire en technologie 90nm CMOS; (iii) amplificateurs faible bruit (LNA) à 60 GHz en technologie standard 65nm CMOS. / The research activity carried out during this PhD consists on the design of radio- frequency integrated circuits, for ultra-wideband (UWB) and millimeter-wave sys- tems, and covers the following topics: (i) radio-frequency integrated circuits for low-power transceivers for wireless local networks; (ii) fully integrated UWB radar for cardio-pulmonary monitoring in 90nm CMOS technology; (iii) 60-GHz low noise amplifer (LNA) in 65nm CMOS technology.

<p>The current consumption of the IQ modulator is a significant part of the totalcurrent consumption of a mobile transmitter platform and reducing it is of greatinterest. Also, as the WCDMA/LTE standards specifies full duplex transmissionsand Tx and Rx are most often using the same antenna, it is crucial to have asolution with low noise generation. Two new proposals have been studied with theaim to reduce the current consumption and noise contribution of the IQ modulator.</p><p>A current mode envelope tracking IQM is the first of the studied designs. Thisimplementation lowers the bias currents in the circuit in relation to the amplitudeof the baseband input signals, meaning that a low input amplitude results in alowering of the current consumption. It proves to be very efficient for basebandsignals with a high peak-to-average ratio. Simulations and calculations have shownthat an average current reduction of 56 % can be achieved for an arbitrary LTEbaseband signal.</p><p>The second is an entirely new passive mixer design where the baseband voltagesare sequentially copied to the RF node, removing the need for V-to-I conversion inthe mixer which reduces current consumption and noise. Results from simulationshas proven that this design is fully capable of improving both current consumptionas well as the noise levels. With an output power of 4.0 dBm, the power consumptionwas 43.3 mW, including clock generating circuits. This, combined with thefact that the design is small and simple, means that there is definitely a possibilityto replace the present IQM design with a passive mixer.</p>

Dans le cadre de la radio logicielle, un transmetteur numérique, basé sur la modulation ΔΣ, est proposé. Son architecture est construite autour de deux modulateurs ΔΣ passe-bas suréchantillonnés du 3ème ordre qui fournissent un signal multiplexé sur 1 bit à haute cadence, qui code directement le signal RF dans le domaine numérique. La séquence de sortie peut ensuite être appliquée à l'entrée d'un amplificateur de puissance commuté ayant une bonne efficacité.<br />Le standard UMTS a été choisi comme exemple d'application et un générateur de signaux RF 1 bit à 7,8Géch/s a été réalisé dans une technologie 90nm CMOS. Une arithmétique redondante comprenant des signaux complémentaires, une quantification de sortie non exacte et une évaluation anticipée de la sortie ont été implémentées pour parvenir à la cadence désirée. Une logique dynamique différentielle sur 3 phases d'horloge, générées par une DLL, a été utilisée au niveau circuit.<br />Le circuit intégré du transmetteur prototype démontre une fonctionnalité complète jusqu'à une fréquence d'horloge de 4GHz, permettant ainsi d'atteindre une bande passante de 50MHz autour d'une fréquence porteuse de 1GHz. Si la bande image est utilisée, la fréquence d'émission peut être déplacée jusqu'à 3GHz. Avec une fréquence d'horloge de 2,6GHz et un canal WCDMA de 5MHz modulé autour d'une fréquence porteuse à 650MHz, 53,6dB d'ACLR sont obtenus pour une puissance de canal en sortie de -3,9dBm. Pour la bande image (1,95GHz), l'ACPR est de 44,3dB pour une puissance maximale du canal en sortie de -15,8dBm, ce qui rentre dans les spécifications UMTS. L'aire active du circuit est de 0,15mm² et sa consommation de 69mW sous 1V à cette fréquence.

Power dissipation of integrated circuits is the most demanding issue for very large scale integration (VLSI) design engineers, especially for portable and mobile applications. Use of multiple supply voltages systems, which employs level converter between two voltage islands is one of the most effective ways to reduce power consumption. In this thesis work, a unique level converter known as universal level converter (ULC), capable of four distinct level converting operations, is proposed. The schematic and layout of ULC are built and simulated using CADENCE. The ULC is characterized by performing three analysis such as parametric, power, and load analysis which prove that the design has an average power consumption reduction of about 85-97% and capable of producing stable output at low voltages like 0.45V even under varying load conditions.

The current consumption of the IQ modulator is a significant part of the totalcurrent consumption of a mobile transmitter platform and reducing it is of greatinterest. Also, as the WCDMA/LTE standards specifies full duplex transmissionsand Tx and Rx are most often using the same antenna, it is crucial to have asolution with low noise generation. Two new proposals have been studied with theaim to reduce the current consumption and noise contribution of the IQ modulator. A current mode envelope tracking IQM is the first of the studied designs. Thisimplementation lowers the bias currents in the circuit in relation to the amplitudeof the baseband input signals, meaning that a low input amplitude results in alowering of the current consumption. It proves to be very efficient for basebandsignals with a high peak-to-average ratio. Simulations and calculations have shownthat an average current reduction of 56 % can be achieved for an arbitrary LTEbaseband signal. The second is an entirely new passive mixer design where the baseband voltagesare sequentially copied to the RF node, removing the need for V-to-I conversion inthe mixer which reduces current consumption and noise. Results from simulationshas proven that this design is fully capable of improving both current consumptionas well as the noise levels. With an output power of 4.0 dBm, the power consumptionwas 43.3 mW, including clock generating circuits. This, combined with thefact that the design is small and simple, means that there is definitely a possibilityto replace the present IQM design with a passive mixer.