Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2004. / Hess, Dennis, Committee Member; Meindl, James, Committee Chair; Allen, Phillip, Committee Member; Cressler, John, Committee Member; Davis, Jeffrey, Committee Member. Vita. Includes bibliographical references (leaves 108-119).

Thesis (Ph. D. in Electrical Engineering)--Vanderbilt University, 2003. / Title from PDF title screen. Includes bibliographical references.

Organic complementary circuits are attracting significant attention due to their high power efficiency and operation robustness, driven by the demands for low-cost, large-area and flexible devices. Previous demonstrations of organic complementary circuits often show high operating voltage, small noise margins, low dc gain, and electrical instability such as hysteresis and threshold voltage shifts. There are two obstacles to developing organic complementary circuits: the lack of high-performance n-channel OFET devices, and the processing difficulty of integrating both n- and p-channel organic field-effect transistors (OFETs) on the same substrate. The operating characteristics of OFETs are often governed by the boundary conditions imposed by the device architecture, such as interfaces and contacts instead of the properties of the semiconductor material. Therefore, the performance of OFETs is often limited if either of the essential interfaces or contacts next to the semiconductor and the channel are not optimized. This dissertation presents research work performed on OFETs and OFET-based complementary inverters in an attempt to address some of these knowledge issues. The objective is to develop high-performance OFETs, with a focus on n-channel OFETs through interface engineering both at the interface between the organic semiconductor and the source/drain electrodes, and at the interface between the organic semiconductor and gate dielectric. Through interface engineering, both p- and n-channel high-performance low-voltage OFETs are realized with high mobilities, low threshold voltages, low subthreshold slopes, and high on/off current ratios. Optimization at the gate dielectric/semiconductor also gives OFET devices excellent reproducibility and good electrical stability under multiple test cycles and continuous electrical stress. Finally, with the interfaces and contacts optimized for both p- and n-channel charge transport, the integration of n- and p-channel OFETs with comparable performance are demonstrated in complementary inverters. The research achieves inverters with a high-gain, a low operation voltage, good electrical stability (absence of hysteresis), and a high switching-speed. A preliminary study of the encapsulation of OFETs and inverters with an additional protective layer is also presented to validate the practicality of organic devices containing air-sensitive n-channel transport.

Thesis (M. S. in Electrical Engineering)--Vanderbilt University, May 2009. / Title from title screen. Includes bibliographical references.

Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2008. / Committee Chair: John D. Cressler; Committee Member: John Papapolymerou; Committee Member: Shyh-Chiang Shen.

Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2005. / Includes bibliographical references. Also available in electronic version.

Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2006. / Includes bibliographical references. Also available in electronic version.

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

abstract: Nanofluidic devices in which one single-walled carbon nanotube (SWCNT) spans a barrier between two fluid reservoirs were constructed, enabling direct electrical measurement of the transport of ions and molecules. Ion current through these devices is about 2 orders of magnitude larger than that predicted from the bulk resistivity of the electrolyte. Electroosmosis drives excess current, carried by cations, and is found to be the origin of giant ionic current through SWCNT as shown by building an ionic field-effect transistor with a gate electrode embedded in the fluid barrier. Wetting of inside of the semi-conducting SWCNT by water showed the change of its electronic property, turning the electronic SWCNT field-effect transistor to "on" state. These findings provide a new method to investigate and control the ion and molecule behavior at nanoscale. / Dissertation/Thesis / Ph.D. Physics 2011

The aggressive scaling of silicon (Si) based complementary metal-oxide-semiconductor (CMOS) transistor over the past 50 years has resulted in an exponential increase in device density, which consequentially has increased computation power rapidly. This has pronounced the necessity to scale the device's supply voltage (VDD) in to order to maintain low-power device operation. However, the scaling of VDD can degrade drive current significantly due to the low carrier mobility of Si. To overcome the key challenges of dimensional and voltage scaling required for low-power electronic operation without degradation of device characteristics, the adoption of alternate channel materials with low bandgap with superior transport properties will play a crucial role to improve the computation ability of the standard integrated circuit (IC). The requirement of high-mobility channel materials allows the industry to harness the potential of III-V semiconductors and germanium. However, the adoption of such high mobility materials as bulk substrates remains cost-prohibitive even today. Hence, another key challenge lies in the heterogeneous integration of epitaxial high-mobility channel materials on the established cost-effective Si platform. Furthermore, dimensional scaling of the device has led to a change in architecture from the conventional planar MOSFET to be modified to a 3-D Tri-gate architecture which provides fully depleted characteristics by increasing the inversion layer area and hence, providing superior electrostatic control of the device channel to address short channel effects such as subthreshold slope (SS) and drain induced barrier lowering (DIBL). The Tri-gate configuration provides a steeper SS effectively reducing leakage current (IOFF), thereby decreasing dynamic power consumption and increasing device performance. Recently, Tantalum silicate (TaSiOx) a high-k dielectric has been shown to exhibit superior interfacial quality on multiple III-V materials. However, there is still ambiguity as to the potential of short-channel devices incorporating alternate channel (III-V) materials which is the basis of this research, to demonstrate the feasibility of future high-mobility n-channel InGaAs material integration on Si for high- speed, low-power, high performance CMOS logic applications. / Master of Science