The aggressive scaling of silicon (Si) based complementary metal-oxide-semiconductor (CMOS) transistor over the past 50 years has resulted in an exponential increase in device density, which consequentially has increased computation power rapidly. This has pronounced the necessity to scale the device's supply voltage (VDD) in to order to maintain low-power device operation. However, the scaling of VDD can degrade drive current significantly due to the low carrier mobility of Si. To overcome the key challenges of dimensional and voltage scaling required for low-power electronic operation without degradation of device characteristics, the adoption of alternate channel materials with low bandgap with superior transport properties will play a crucial role to improve the computation ability of the standard integrated circuit (IC). The requirement of high-mobility channel materials allows the industry to harness the potential of III-V semiconductors and germanium. However, the adoption of such high mobility materials as bulk substrates remains cost-prohibitive even today. Hence, another key challenge lies in the heterogeneous integration of epitaxial high-mobility channel materials on the established cost-effective Si platform. Furthermore, dimensional scaling of the device has led to a change in architecture from the conventional planar MOSFET to be modified to a 3-D Tri-gate architecture which provides fully depleted characteristics by increasing the inversion layer area and hence, providing superior electrostatic control of the device channel to address short channel effects such as subthreshold slope (SS) and drain induced barrier lowering (DIBL). The Tri-gate configuration provides a steeper SS effectively reducing leakage current (IOFF), thereby decreasing dynamic power consumption and increasing device performance. Recently, Tantalum silicate (TaSiOx) a high-k dielectric has been shown to exhibit superior interfacial quality on multiple III-V materials. However, there is still ambiguity as to the potential of short-channel devices incorporating alternate channel (III-V) materials which is the basis of this research, to demonstrate the feasibility of future high-mobility n-channel InGaAs material integration on Si for high- speed, low-power, high performance CMOS logic applications. / Master of Science

Low-frequency noise has been measured on commercial power MOSFETs. These devices, fabricated with the VDMOS structure, exhibit a 1/f type noise spectrum. The interface state density obtained from noise measurements was compared with that obtained from the subthreshold-slope method. Reasonable agreement was found between the two measurements. The radiation effects on the noise power spectral density were also investigated. The results indicated that the noise can be attributed to the generation of interface traps near the Si-SiO₂ interface. The level of interface traps generated by radiation was bias dependent. The positive gate bias gave rise to the largest interface-trap density.

published_or_final_version / Electrical and Electronic Engineering / Doctoral / Doctor of Philosophy

published_or_final_version / abstract / Electrical and Electronic Engineering / Master / Master of Philosophy

The very low photon backgrounds to be achieved by future cryogenic astronomical telescopes present the ultimate challenge to the sensitivity of infrared detectors and associated readout electronics. Cooled silicon JFETs, operated around 70 K in transimpedance amplifiers, have shown excellent performance and stability. However, due to Johnson noise in the feedback resistor, the read noise in one second achieved by such amplifiers is about 500 electrons per second. A drastic improvement in sensitivity was demonstrated using a simple form of integrating JFET amplifiers. Therefore, the excellent performance obtained with cooled silicon JFETs has led to the investigation of their properties in the temperature range 33-77 K to explore their full potential and improve the performance of the integrating amplifier. The freezeout effect in silicon JFETs has been characterized both experimentally and theoretically using a simple analytical simulation program. The effect of variation in device parameters on the freezeout characteristic has been studied, and test results showed that an effective channel mobility must be used instead of a bulk mobility in order to simulate accurately the device current and transconductance freezeout at low temperatures. Many types of commercially available JFETs have been characterized below 77 K and measurements revealed that a balanced source follower or a common-source amplifier with active load can operate well down to 38 Kelvin with extremely low power dissipation. The open gate equivalent input noise voltage was found to be optimum below 77 K, due to a decrease in the gate leakage current, in agreement with theoretical prediction. Based on the superior performance of the balanced source follower with active load, a single channel hybrid integrating JFET amplifier with a JFET reset and a compensation capacitor was developed for operation in the temperature range 40-77 K. Read noise as low as 10 electrons in 128 seconds integration was achieved when the integrator was operated at an optimum temperature of about 55 K. Using a similar design, a 16-channel monolithic integrating amplifier array was designed and built. Preliminary test results at 77 K showed noise performance comparable to the single channel hybrid integrator.

The LAMBDA-DIODE was invented in integrated-circuit form in 1974. There was a proposal about this device's application in memory circuits at that time. This thesis is to evaluate the circuit performance of the COMPLEMENTARY JFET LAMBDA-DIODE SRAM. It investigates the speed, power consumption and chip area of this circuit compared with the JFET CROSS COUPLED SRAM by using SPICE and breadboard simulation techniques. The results show positive signs of the Λ-DIODE's feasibility for use in VLSI static memory circuits from the chip area aspect if the parasitic capacitance of the JFET device could be minimized to reduce the power delay product.

Experiments were conducted on current-mirror MOSFETs to examine their suitability for use in radiation environments. These devices, which allow low loss load current sensing (defined by a current-ratio n'), are an important element of many power integrated circuits (PICs). Total-dose testing demonstrated that the current ratio was virtually unaffected for many operating conditions. In all cases, changes were largest when sense resistance was largest and minimal when sense voltage was approximately equal to the load source's voltage. In addition, testing verified the feasibility of using sense-cell MOSFETs for applications which require radiation exposure. A constant-current op-amp circuit showed minimal current shifts, using proper circuit design, following total-dose exposure. Dose-rate testing showed the feasibility of using sense voltage to trigger g&d2; protection through drain-source voltage clamping, providing a relatively inexpensive alternative to voltage derating.

Fast neutron irradiation tests were performed to determine the correlation of change of drain-source resistance and neutron fluence for power MOSFETs. The Objectives of the tests were: (1) to detect and measure the degradation of critical MOSFET device parameters as a function of neutron fluence (2) to compare the experimental results and the theoretical model. In general, the drain-source resistance increased from 1 Ohm to 100 Ohm after exposure to fast neutron fluence of 3 x 1014 neut/cm2, and decreased by a factor of five after high temperature annealing.

Many high performance amplifiers use power MOSFETs in their output stages, especially in operational amplifier applications whenever high current or power is needed. MOSFETs have advantages over bipolar transistors in amplifier output stage because MOSFETs are majority carrier devices. The result is wide frequency response, fast switching and better linearity than power bipolar transistors. But unlike bipolar circuits, which are relatively tolerant of ionizing radiation, MOSFETs may suffer severe parametric degradation at low total-dose levels. The effects of ionizing radiation on MOSFETs are discussed, and the performance of an amplifier circuit that uses a complementary MOSFET source follower in its output stage is simulated to examine the effect of MOSFET radiation damage on amplifier performance. An increase in power dissipation was the most significant degradation caused by ionizing radiation.

The discovery of semi-conducting and conducting organic materials has opened new possibilities for electronic devices and systems. Applications, previously unattainable for conventional electronics, have become possible thanks to the development of conjugated polymers. Conjugated polymers that are both ion- and electron conducting, allow for electrochemical doping and de-doping via reversible processes as long as both forms of conduction remain available. Doping causes rearrangement of the -system along the polymer backbone, and creates new states in the optical band gap, resulting in an increased electronic conductivity and also control of the color (electrochromism). Doping can also occur by charge injection at a metal – semiconducting polymer interface. Electrochemical electronic devices and solid state devices based on these two types of doping are now beginning to enter the market. This thesis deals with organic based-devices whose working mechanism involves electrolytes. After describing the properties of conjugated polymers, fundamentals on electrolytes (ionic conductivity, types, electric double layer and the electric field distribution) are briefly presented. Thereafter, a short review of the field of organic field effect transistors as well as a description of transistors that are gated via an electrolyte will be reviewed. Paper I present a novel technique to visualize the electric field within a two-dimensional electrolyte by applying the electrolyte over an array of electronically isolated islands of electrochromic polymer material on a plastic foil. By observing the color change within each polymer island the direction and the magnitude of the electric field can be measured. This technology has applications in electrolyte evaluation and is also applicable in bio-analytical measurements, including electrophoresis. The focus of paper II lies on gating an organic field effect transistor (OFET) by a polyanionic proton conductor. The large capacitance of the electric double layer (EDL) that is formed at organic semiconductor/polyelectrolyte upon applying a potential to the gate, results in low operation voltages and fast response. This type of transistor that is gated via electric double layer capacitor is called EDLC-OFET. Because an electrolyte is used as a gate insulator, the role of the ionic conductivity of the electrolyte is considered in paper III. The effect on the electronic performance of the transistor is studied as well by varying the humidity level.