Two graphene layers placed in close proximity offer a unique system to investigate interacting electron physics as well as to test novel electronic device concepts. In this system, the interlayer spacing can be reduced to value much smaller than that achievable in semiconductor heterostructures, and the zero energy band-gap allows the realization of coupled hole-hole, electron-hole, and electron-electron two-dimensional systems in the same sample. Leveraging the fabrication technique and electron transport study in dual-gated graphene field-effect transistors, we realize independently contacted graphene double layers separated by an ultra-thin dielectric. We probe the resistance and density of each layer, and quantitatively explain their dependence on the backgate and interlayer bias. We experimentally measure the Coulomb drag between the two graphene layers for the first time, by flowing current in one layer and measuring the voltage drop in the opposite layer. The drag resistivity gauges the momentum transfer between the two layers, which, in turn, probes the interlayer electron-electron scattering rate. The temperature dependence of the Coulomb drag above temperatures of 50 K reveals that the ground state in each layer is a Fermi liquid. Below 50 K we observe mesoscopic fluctuations of the drag resistivity, as a result of the interplay between coherent intralayer transport and interlayer interaction. In addition, we develop a technique to directly measure the Fermi energy in an electron system as a function of carrier density using double layer structure. We demonstrate this method in the double layer graphene structure and probe the Fermi energy in graphene both at zero and in high magnetic fields. Last, we realize dual-gated bilayer graphene devices, where we investigate quantum Hall effects at zero energy as a function of transverse electric field and perpendicular magnetic field. Here we observe a development of v = 0 quantum Hall state at large electric fields and in high magnetic fields, which is explained by broken spin and valley spin symmetry in the zero energy Landau levels. / text

Dans la lignée des progrès technologiques récents en électronique, ces dernières décennies ont vu l’émergence d’une variété de systèmes permettant l’interface bioélectronique, allant de la mesure de l’activité électrique émise par l’ensemble du cerveau jusqu’à la mesure du signal émis par un neurone unique. Bien que des interfaces électroniques avec les neurones ont montré leur utilité pour des applications cliniques et sont communément utilisés par les neurosciences fondamentales, leurs performances sont encore très limitées, notamment en raison de l’incompatibilité relative entre les systèmes à l’état solide et le vivant. Dans ce travail de thèse, nous avons étudié des techniques et des matériaux nouveaux permettant une approche alternative et qui pourraient améliorer le suivi de l’activité de réseaux de neurones cultivés in situ et à terme la performance des neuroprothèses in vivo. Dans ce travail, des réseaux de nanofils de silicium et des microélectrodes en diamant sont élaborés pour respectivement améliorer la résolution spatiale et la stabilité des électrodes dans un environnement biologique. Un point important de cette thèse est également l’évaluation des performances de transistors à effet de champ en graphène pour la bio électronique. En raison des performances remarquables et combinées sur les aspects électrique, mécanique et chimique du graphène, ce matériau apparaît comme un candidat très prometteur pour la réalisation d’une électronique permettant une interface stable et sensible avec un réseau de neurones. Nous montrons dans ce travail l’affinité exceptionnelle des neurones avec une surface de graphène brut et la réalisation d’une électronique de détection rapide et sensible à base de transistor en graphène. / In line with the technological progress of last decades a variety of adapted bioelectrical interfaces was developed to record electrical activity from the nervous system reaching from whole brain activity to single neuron signaling. Although neural interfaces have reached clinical utility and are commonly used in fundamental neuroscience, their performance is still limited. In this work we investigated alternative materials and techniques, which could improve the monitoring of neuronal activity of cultured networks, and the long-term performance of prospective neuroprosthetics. While silicon nanowire transistor arrays and diamond based microelectrodes are proposed for improving the spatial resolution and the electrode stability in biological environment respectively, the main focus of this thesis is set on the evaluation of graphene based field effect transistor arrays for bioelectronics. Due to its outstanding electrical, mechanical and chemical properties graphene appears as a promising candidate for the realization of chemically stable flexible electronics required for long-term neural interfacing. Here we demonstrate the outstanding neural affinity of pristine graphene and the realization of highly sensitive fast graphene transistors for neural interfaces.

Cette thèse porte sur l'étude d'un diélectrique de type ferroélectrique pour une application aux transistors organiques. La configuration adoptée est de type bottom-gate top- contact. Le matériau semi-conducteur utilisé est un transporteur d'électrons. Dans la première partie de ce projet, nous avons réalisé des transistors organiques à effet de champ (OFETs) avec une couche de PMMA comme diélectrique de grille. Ce matériau, très étudié et connu, permet d'avoir un composant servant de référence. Nous avons également mené une étude sur la longueur de canal, la vitesse de dépôt du semi-conducteur organique et l'épaisseur du diélectrique, en vue d'en déduire l'influence de ces grandeurs sur les performances électriques des OFETs. Après l'optimisation de ces paramètres, nous avons démontré une amélioration de la mobilité des porteurs, une augmentation du rapport Ion/Ioff, une amélioration de la capacité et une diminution des tensions d'alimentation et de seuil. Ces résultats ont été interprétés à l'aide de caractérisations électriques. Dans un second temps, le diélectrique ferroélectrique poly(vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) a été ajouté au composant, afin de réaliser un diélectrique hybride avec le PMMA. Ce dernier permet de combiner les avantages de la haute permittivité relative du P(VDF-TrFE), et de la faible rugosité du film de PMMA en contact avec le semiconducteur. Une étude comparative a été effectuée avec les transistors de référence. Il en ressort, pour une épaisseur identique de diélectrique, une diminution des tensions d'alimentation et de seuil, et une amélioration de la mobilité des charges avec l'OFET implémentant le matériau ferroélectrique. La discussion de ces résultats est appuyée par des caractérisations électriques et morphologiques. / This thesis deals with the study of a ferroelectric material as gate dielectric for organic transistor applications. The configuration adopted is bottom-gate top-contact. The semiconductor used is an electron transport material. In a first part, we made organic field effect transistors (OFETs) with a layer of PMMA as a gate dielectric. This material, very studied and well known, serves as reference. We also carried out a study on the channel length, the organic semiconductor deposition rate and the dielectric thickness, in order to deduce the impact of these parameters on OFETs performances. After optimization, we have demonstrated an improvement of the mobility, on/off current ratio, capacitance and a reduction of supply and threshold voltages. These results have been interpreted using electrical characterizations. In a second step, the poly (vinylidenefluoride-co- trifluoroethylene) (P(VDF-TrFE)) ferroelectric material was added to provide a hybrid dielectric with PMMA. This OFET combine the advantages of high permittivity of P(VDF-TrFE) and low roughness of PMMA. A comparative study was carried out with reference transistors. For same dielectric thickness, a reduction of the supply and threshold voltages and an improvement of the mobility is obtained for the OFET implementing ferroelectric material. The discussion of these results is supported by electrical and morphological characterizations.

Les nanostructures de semi-conducteurs de faibles dimensions (comme les nanofils(NFs)) sont devenues l'objet de recherches intensives pour explorer de nouveaux phénomènes émergents à l'échelle nanométrique et sonder leur possibilités d’ utilisation dans l'électronique du futur. Parmi les différents nanofils semi-conducteurs, SiC a des propriétés très particulières, comme une large bande interdite, une excellente conductivité thermique, un haut champ électrique de claquage, une stabilité chimique et physique, une haute mobilité des électrons et une haute biocompatibilité.Nous proposons dans cette étude ; d'examiner une nouvelle approche pour fabriquer des nanostructures de SiC par l'approche « top-down ». Cela permet l'élaboration de nanostructures cristallines de SiC de haute qualité monocristalline avec un niveau de dopage contrôlé. Le comportement de nanostructures de SiC gravées a également été étudié en fonction de polytypes et des orientations cristallographiques.Nous avons également étudié les trois principaux sujets de SiC nano-devices pour atteindre une excellente performance. Pour répondre à ces questions, deux types de SiC nanoFET (SiC NFFET et SiC NPFET) ont été fabriqués et caractérisés par l'utilisation de nanofils de SiC et de nanopiliers de SiC préparés respectivement par les méthodes « bottom-up » et « top-down ». / Low dimensional semiconductor nanostructures, such as nanowires (NWs), have become the focus of intensive research for exploring new emergent phenomena at the nanoscale and probing their possible use in future electronics. Among these semiconductor NWs, Silicon Carbide (SiC) has very unique properties, such as wide bandgap, excellent thermal conductivity, chemical and physical stability, high electron mobility and biocompatibility. These factors makes SiC a long standing candidate material to replace silicon in specific electronic device applications operating in extreme conditions or/and harsh environments. SiC nanostructures have been studied extensively and intensively over the last decade not only for their fabrication and characterization, but also for their diverse applications. I have outlined the growth of SiC nanostructures based on different growth methods, a noteworthy feature of their characteristic properties and potential applications in the chapter one. As-grown SiC NWs fabricated by bottom-up method present a high density of structural defects, such as stacking faults. This kind of defect is one of the factors which lead to poor electrical performance (such as weak gate effect and low mobility) of the related devices. Therefore, it is required to develop a high quality of SiC nanostructures with low density of the structural defects using an alternative method, such as top-down process. Main objectives of this thesis are divided into three main parts. The first part of the thesis (Chapter two), we present the simulation results of the electrical transport and thermoelectric properties of SiC NWs. I have investigated the thermoelectric enhancement by studying the complex interplay of the size of NWs, temperature and surface roughness. Our simulation results show that the ZT of C terminated SiC NW (2.05×2.05 nm2) reaches a maximum value of 1.04 at 600K. The second part of the thesis (Chapter there) is devoted to the fabrication of high quality SiC nanostructures with controlled doping level. I have developed a top-down fabrication technique for high quality nanometer scale SiC nanopillars (NPs) using inductively coupled plasma etching. The etching behavior of SiC NPs has also been studied depending on polytypes and crystallographic orientations. Under the optimal etching conditions using a large circular mask pattern with 370 nm diameter, the obtained 4H-SiC nanopillars exhibit high anisotropy features (6.4) with a large etch depth (>7μm). A hexagonal, rhombus and triangle based pillar structures have been obtained using α-SiC (0001), 3C-SiC (001) and 3C-SiC (111) substrates, respectively. The last part of the thesis (Chapter four) is dedicated to the design and the electrical characterization of SiC nanodevices. To investigate the electrical properties of SiC nanostructures, two different kinds of SiC nanoFETs (SiC NWFET and SiC NPFET) have been fabricated by using SiC NWs and SiC NPs prepared via bottom-up method and top-down methods, respectively. In case of SiC NWFET, low resistivity ohmic contacts (378 kΩ) have been obtained after the annealing at 650 °C. Ni silicide intrusion into the SiC NW channel has been observed the annealing at 700 °C. This temperature is compared to one of other group IV materials. In case of SiC NPFET, two different types of NPFET (3C-SiC (001) and 4H-SiC (0001)) have been fabricated using our SiC nanopillars, obtained by top-down approach. The estimated values of the field-effect carrier mobility are 232.7 cm2⋅V-1s-1 for 3C-SiC (001) NPFET (#2) and 53.6 cm2⋅V-1s-1 for 4H-SiC (0001) NPFET, which is higher than the best values reported in the literature (15.9 cm2⋅V-1s-1).

In recent years, the use of first-principles based atomistic modeling technique has become extremely popular to gain better insights on the various locally modulated electronic properties of nano materials and structures. Atomistic modeling offers the benefit of predicting crystal structures, visualizing orbital distribution and electron density, as well as understanding material properties which are hard to access experimentally. The single layer MoS2 has emerged as a suitable choice for the next generation nano devices, owing to its distinctive electrical, optical and mechanical properties like, better electrostatics, increased photo luminescence, higher mechanical flexibility, etc. The realization of decananometer scale digital switches with the single layer MoS2 as the channel may provide many significant advantages such as, high On/Off current ratio, excellent electrostatic control of the gate, low leakage, etc. However, there are quite a few critical issues such as, forming low resistance source/drain contacts, achieving higher effective mobility, ensuring large scale controlled growth, etc. which need to be addressed for successful implementation of the atomically thin transistors in integrated circuits. Recent experimental demonstration showing the coexistence of metallic and semiconducting phases in the same monolayer MoS2, has attracted much attention for its use in ultra-low contact resistance-MoS2 transistors. Howbeit, the electronic structures of the metallic-to-semiconducting phase boundaries, which appear to dictate the carrier injection in such transistors, are not yet well understood. In this work, we first develop the geometrically optimized atomistic models of the 2H-1T′ hetero-phase structures with two distinct phase boundaries, β and γ. We then apply density functional theory to calculate the electronic structures for those optimized geometries. Furthermore, we employ non equilibrium Green’s function formalism to evaluate the transmission spectra and the local density of states in order to assess the Schottky barrier nature of the phase boundaries. Nonetheless, the symmetry of the source-channel and drain-channel junction, is a unique property of a metal-oxide semiconductor field effect transistor (MOSFET), which needs to be preserved while realizing sub-10 nm channel length devices using advanced technology. Employing experimental-findings-driven atomistic modeling technique, we demonstrate that such symmetry might not be preserved in an atomically thin phase-engineered MoS2- based MOSFET. It originates from the two distinct atomic patterns at phase boundaries (β and β*) when the semiconducting phase (channel) is sandwiched between the two metallic phases (source and drain). Next, using first principles based quantum transport calculations we demonstrate that due to the clusterization of “Mo” atoms in 1T′ MoS2, the transmission along the zigzag direction is significantly higher than that in the armchair direction. Moreover, to achieve excellent impedance matching with various metal contacts (such as, “Au”, “Pd”, etc.), we further develop the atomistic models of metal-1T′ MoS2 edge contact geometries and compute their resistance values. Other than the charge carrier transport, analysing the heat transport across the channel is also crucial in designing the ultra-thin next generation transistors. Hence, in this thesis work, we have investigated the electro-thermal transport properties of single layer MoS2, in quasi ballistic regime. Besides the perfect monolayer in its pristine form, we have also considered various line defects which have been experimentally observed in mechanically exfoliated MoS2 samples. Furthermore, a comprehensive study on the phonon thermal conductivity of a suspended monolayer MoS2, has been incorporated in this thesis. The studies presented in this thesis could be useful for understanding the carrier transport in atomically thin devices and designing the ultra-thin next generation transistors.

A eletrônica digital desempenha papel essencial no desenvolvimento e manutenção dos padrões de vida em prática hoje no mundo. A peça fundamental para a criação desta era tecnológica é sem dúvidas o transistor. Com o advento de novos materiais, a busca por transistores que oferecem novas oportunidades de processamento e aplicação permitiu que uma nova área fosse criada: a eletrônica orgânica. Transistores de efeito de campo baseados em filmes finos de materiais orgânicos têm recebido grande atenção nas últimas décadas. Apresentamos um estudo experimental e teórico de transistores de efeito de campo a base de filmes finos orgânicos. Foram caracterizados transistores usando um derivado do pentaceno (TMTES-pentaceno) como camada ativa em um dispositivo feito sobre Si/SiO2. Mostramos que a inclusão do semicondutor orgânico em uma matriz polimérica isolante ajuda a manter a estabilidade termo mecânica do dispositivo. Foi desenvolvido um modelo que levasse em conta as resistências parasíticas para explicar o comportamento do transistor em função da temperatura. Também foram construídos e caracterizados transistores usando rr-P3HT como semicondutor e PMMA como isolantes. Apresentamos transistores do tipo Top-Gate e Bottom-Gate com mobilidade máxima de 7 x 10-3 cm2/V.s. Valores de razão ON/OFF de ~ 900 foram encontrados nos transistores otimizados. O comportamento dos transistores é analisado em função da temperatura e os modelos de aproximação de canal gradual e de Vissenberg-Matters foram aplicados para extração dos parâmetros de interesse. Por fim, apresentamos um modelo de corrente de canal baseado na resolução 2D numérica da equação de Poisson usando as idéias de Vissenberg-Matters para a concentração de cargas em função do potencial local. O modelo, embora ainda nos primeiros estágios de desenvolvimento, prevê a saturação da corrente nas curvas de saída simuladas sem limitações de regime de validade. / Digital electronics plays an essential role in the development and maintenance of living standards into practice in the world today. The cornerstone for the creation of this technological age is undoubtedly the transistor. With the advent of new materials, the search for transistors that offer new opportunities in processing and application allowed a new area to be created: the organic electronics. Field effect transistors based on organic thin films have received great attention in recent decades. We report an experimental and theoretical study of field effect transistors based on organic thin films. We characterized transistors manufactured using a derivative of pentacene (TMTES-pentacene) as the active layer in a device and using Si/SiO2 as gate and insulator. We show that the inclusion of the organic semiconductor in an insulating polymeric matrix helps to maintain the termo-mechanical stability of the device. A model was developed that take into account the parasitic resistances and to explain the behavior of the transistor as a function of temperature. We also present the manufacturing and characterization process of transistors using rr-P3HT as semiconductor and PMMA as insulator. We report Top-Gate and Bottom-Gate transistors with maximum mobility of 7 x 10-3 cm2/V.s. The maximun ON/OFF ratio of ~ 900 was found for the optimized transistors. The behavior of the transistors was analyzed as a function of temperature and both gradual channel approximation and Vissenberg-Matters models were applied for extracting the parameters. Finally, we present a channel current model based on the resolution of 2D numerical Poisson equation using the ideas of Vissenberg-Matters to the calculate the concentration of charges due to the local potential. The model, although still in the early stages of development, predicts the saturation current at output simulated curves with no limitation of regime validity.

Orientador: Carlos Alberto dos Reis Filho / Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação / Made available in DSpace on 2018-08-07T11:14:24Z (GMT). No. of bitstreams: 1 Couto_AndreLuisdo_M.pdf: 2940356 bytes, checksum: 959908541a3bc46b7b7035eb035de186 (MD5) Previous issue date: 2005 / Resumo: A integração de memórias e circuitos analógicos em um mesmo die oferece diversas vantagens: redução de espaço nas placas, maior confiabilidade, menor custo. Para tanto, prescindir-se de tecnologia específica à confecção de memórias e utilizar-se somente de tecnologia CMOS convencional é requisito para tal integração. Essa pode ser tanto mais eficiente quanto maior a capacidade de armazenagem de dados, ou seja, maior a densidade de informação. Para isso, memórias analógicas mostram-se bem mais adequadas, posto que em uma só célula (um ou dois transistores) podem ser armazenados dados que precisariam de diversas células de memórias digitais e, portanto, de maior área. Neste trabalho, transistores MOS com porta flutuante mostraram-se viáveis de serem confeccionados e resultados de caracterização como tipos de programação, retenção de dados e endurance foram obtidos. O trabalho apresenta as principais características dos FGMOS (Floating Gate MOS) e presta-se como referência à futuros trabalhos na área / Abstract:Monolithic integration of memories and analog circuits ,in the same die offers interesting advantages like: smaller application boards, higher robustness and mainly lower costs. Today, a profitable integration of these kind of circuit can only be possible using conventional CMOS technology, which allows efficiently extraordinary levels of integration. Thus, the possibility of integrating analog memories looks more suitable since one single cell (usually use one or two transistors) serves for storing the same data stored by few digital memory cells, therefore, they requiring less area. In this work, it was implemented different memory cells together with few devices using floating gate MOS transistors and manufactured by a conventional CMOS technology. Differemt sort of programrning', data retention, and endurance were characterized as well as the main characteristics of the FGMOS (Floating Gate MOS) were obtained. The results of their characterization reveal that is possible to make and' to program fIoating gate MOSFETS analog memories and must serve as starting-point and reference for new academic studies / Mestrado / Eletrônica, Microeletrônica e Optoeletrônica / Mestre em Engenharia Elétrica

Cette thèse vise à développer un capteur d’ions cuivre dans des échantillons humains tels que le plasma ou les urines où l’accumulation des ions induit la maladie de Wilson. Le manque d’outil de diagnostic efficace et non invasif rend cette maladie traitable, potentiellement fatale. Notre capteur, basé sur la technologie des transistors à effet de champ de type metal-oxide-semiconducteur, a l’originalité d’utiliser une monocouche de lipide de type DC8,9PC de 2.4 nm d’épaisseur comme diélectrique de grille. Nous démontrons dans cette thèse que ces lipides peuvent être chimiquement modifiés en de monocouches, à stabilité mécanique et électrique élevée, transformées en sondes spécifiques par greffage sur le groupement de tête des lipides d’une fonction chélatante spécifique aux ions cuivre. La monocouche lipidique est formée à la surface du canal semiconducteur du transistor par fusion vésiculaire et est stabilisée par réticulation des lipides suivant un protocole que nous avons développé. Dans une première partie, nous décrivons la fabrication du transistor ainsi que l’ingénierie chimique des lipides avec le chélateur. Des mesures, en solutions aqueuses contenant des ions cuivre et d’autres ions potentiellement compétiteurs, ont validé la sensibilité et la spécificité du capteur. La deuxième partie est dédiée à l’optimisation des monocouches en tant qu’isolants électriques stables. Nous introduisons dans cette thèse la notion de double polymérisation des lipides dans la monocouche avec réticulation des chaînes aliphatiques et des groupements de tête. Nous démontrons que celle-ci conduit à l’amélioration drastique des propriétés mécaniques et électriques des monocouches. / This thesis aims at developing a sensor for the detection of Cu2+ in human samples such as urine. Copper is an ion of pathological interest in the body and its accumulation in tissues is responsible for the Wilson disease. While the disease can be effectively treated, the lack of efficient and non-invasive diagnosis techniques makes it potentially deadly. Our project aims for developing an efficient, sensitive, specific, and low cost sensor device based on metal-oxide-semiconductor field effect transistor technology and has the originality of using a 2.4 nm thick monolayer of DC8,9PC lipids as gate dielectric. We demonstrate that such lipids can be chemically engineered to allow the fabrication of monolayers with high mechanical and electrical stability and to confer them specific probe function. Specificity of the sensor is given by the grafting of a copper specific chelator to the lipids head-groups. The lipid monolayer is formed on the transistor semiconducting channel by the vesicle fusion. In the first part of the thesis, we describe the fabrication of the transistor including the chemical engineering of the lipids with the chelator. Sensitivity and specificity measurements were realized in aqueous solutions containing copper ions and potentially competitive ions. The second part is dedicated to improving the performances of the lipid monolayer as a stable insulator. We introduce in this thesis the concept of double polymerization of the lipids in the monolayer with a reticulation at both the levels of their aliphatic chains and their head-groups. We demonstrate that that leads to drastic improvements of both the mechanical and electrical properties of the monolayer.

When a temperature differential is applied across a semiconductor, a thermal voltage develops across it in response. The ratio of this thermal voltage to the applied temperature differential is the Seebeck coefficient, a transport coefficient that complements measurements of electrical and thermal conductivity. The physical interpretation of the Seebeck coefficient is the entropy per charge carrier divided by its charge and is hence a direct measurement of the carrier entropy in the solid state. This PhD thesis has three major outcomes. The first major outcome is a demonstration of how the Seebeck coefficient can be used as a tool to quantify the role of energetic disorder in organic semiconductors. To this end, a microfabricated chip was designed to perform accurate measurements of the Seebeck coefficient within the channel of the active layer in a field-effect transistor (FET). When measured within an FET, the Seebeck coefficient can be modulated using the gate electrode. The extent to which the Seebeck coefficient is modulated gives a clear idea of charge carrier trapping and the distribution of the density of states within the organic semiconductor. The second major outcome of this work is the observation that organic semiconducting polymers show Seebeck coefficients that are temperature independent and strongly gate voltage modulated. The extent to which the Seebeck coefficient is modulated in the polymer PBTTT is found to be larger than that in the polymer IDTBT. Taken together with conventional charge transport measurements on IDTBT, the voltage modulated Seebeck coefficient confirms the existence of a vanishingly small energetic disorder in this material. In the third and final outcome of this thesis, the magnitude of the Seebeck coefficient is shown to be larger for organic small molecules as compared to organic polymers. The basis for this is not yet clear. There are reports that such an observation is substantiated through a larger contribution from vibrational entropy that adds to the so called entropy-of-mixing contribution so as to boost the magnitude of the Seebeck coefficient in organic small molecules. As of now, this remains an open question and is a potential starting point for future work. The practical implications of this PhD thesis lie in building cost-effective and environmentally friendly waste-heat to useful energy converters based on organic polymers. The efficiency of heat to energy conversion by organic polymers tends to be higher than that for conventional semiconductors owing to the presence of narrow bands in organic polymer semiconductors.

This doctoral thesis is focused on the preparation of graphene layers by Chemical Vapor Deposition (CVD) and their utilization for fabrication and characterization of field effect transistors. The theoretical part of the thesis deals with different methods of graphene production and measurement of its transport properties. In the first part of the experimental section the growth of polycrystalline graphene and individual graphene crystals with sizes up to 300 m is investigated. Further, graphene layer was also grown on an atomically flat copper foils, which were fabricated in order to achieve the growth of graphene of higher quality. Subsequently, the transport properties of field effect transistors produced from the grown layers were measured. The last two chapters deal with a doping of graphene layer by gallium atoms and X-ray radiation. Whereas the deposition of gallium atoms on the graphene surface causes chemical doping of graphene layer by charge transfer, X-ray irradiation of graphene field effect transistors induces the ionization of positively charged defects in dielectrics, which electrostatically dope a graphene layer.