Atomically thin Molybdenum disulfide, MoS2, a star member of the group VI transition metal dichalcogenide(TMDC) family has been attracting rising interests for its potential applications in emerging electronics and optoelectronics. Bulk MoS2is a semiconductor with an indirect gap located between the top of valence band at Γ points and the bottom of conduction band in mid of K and Γ points in its Brillouin zone. Atomically thin MoS2 films including monolayers and multilayers, being chemically inert, present a class of intrinsic 2D semiconductors which are widely regarded as a platform for ultimate electronics. As yet tremendous efforts focus on the optical properties and electric transport study. In this thesis, we report the experimental study of photocurrent measurements on MoS2thin films. The sample preparation, device fabrication, optical and electric characterizations are introduced. The experiments have been carried out on a field effect transistor (FET) structured MoS2 device. The photocurrent spectroscopy reveals the interband excitonic transitions at spin-split bands around K valleys. The results demonstrate that MoS2has potential applications in optoelectronics. / published_or_final_version / Physics / Master / Master of Philosophy

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The performance scaling of metal-oxide-semiconductor field-effect-transistors (MOSFETs) has been historically achieved through shrinking the gate length of transistors for over four decades. Addressing the current challenges with CMOS scaling, the 2005 edition of International Technology Roadmap for Semiconductors has predicted the need for so-called technology boosters involving new materials for the gate dielectric and the channel as well as innovative structures. Theoretical studies suggest that the incorporation of high-mobility channel materials such as germanium and III-Vs could outperform bulk Si technology in terms of switching characteristics. Hence, this has recently led to tremendous research activity to explore the prospects of III-V materials for CMOS applications. Nevertheless, technological challenges such as formation of highquality interface between gate dielectric and III-V channel have hindered the demonstration of enhancement-mode III-V MOSFETs. Hence, tremendous effort has been devoted to study the exact origin of Fermi level pinning at the oxide/III-V interface. On the other hand, the advent of high-k materials has opened up the possibility of exploring new channel materials, for which it is challenging to achieve high-quality interface analogous to that of SiO2 on Si. Lately, III-Vs have been extensively explored in order to find compatible gate dielectrics which can unpin the Fermi level at the interface. Amongst various schemes, atomic layer deposition of high-k dielectrics offers some unique advantages such as reduction of GaAs interfacial oxides upon high-k deposition through an appropriate choice of precursor chemistry. The chief focus of this dissertation is to develop a simple wet clean process prior to high-k deposition, suitable for III-V substrates. The impact of various chemical treatments of GaAs substrates on the properties of high-k/GaAs interface was studied through extensive material and electrical characterization methods. The suitability of the ALD-grown high-k gate dielectrics on GaAs for MOSFET fabrication was explored. Charge trapping was found to result in significant errors in mobility extraction in high-k GaAs interface, where the role of high-k is not well understood. Hence, pulsed I-V and QV measurements and galvanomagnetic effects were utilized in order to directly measure the inversion charge in the channel without being affected by the charge traps as much as possible. It was also found that the material studies on GaAs substrates can be readily extended to other III-V channels, such as InGaAs. / text

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