Thesis (Ph. D.)--University of Texas at Austin, 2008. / Vita. Includes bibliographical references.

No description available.

Thesis (M.S.)--Rutgers University, 2009. / "Graduate Program in Electrical and Computer Engineering." Includes bibliographical references (p. 113-116).

Thesis (M.S.)--Boise State University, 2009. / Includes abstract. Includes bibliographical references (leaves 93-95).

Thesis (M.S.)--Boise State University, 2009. / Title from t.p. of PDF file (viewed Mar. 12, 2010). Includes abstract. Includes bibliographical references (leaves 93-95).

Thesis (M.Phil.)--Hong Kong University of Science and Technology, 2003. / Includes bibliographical references. Also available in electronic version. Access restricted to campus users.

Thesis (M.S.)--California Polytechnic State University, 2008. / Major professor: Fei Wang, Ph.D. "Presented to the faculty of California Polytechnic State University, San Luis Obispo." "In partial fulfillment of the requirements for the degree [of] Master of Science in Electrical Engineering." "May 2008." Includes bibliographical references (leaves 53-56). Also available online. Also available on microfiche ( sheet).

Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2005. / Includes bibliographical references. Also available in electronic version.

abstract: Flash memories are critical for embedded devices to operate properly but are susceptible to radiation effects, which make flash memory a key factor to improve the reliability of circuitry. This thesis describes the simulation techniques used to analyze and predict total ionizing dose (TID) effects on 90-nm technology Silicon Storage Technology (SST) SuperFlash Generation 3 devices. Silvaco Atlas is used for both device level design and simulation purposes. The simulations consist of no radiation and radiation modeling. The no radiation modeling details the cell structure development and characterizes basic operations (read, erase and program) of a flash memory cell. The program time is observed to be approximately 10 μs while the erase time is approximately 0.1 ms. The radiation modeling uses the fixed oxide charge method to analyze the TID effects on the same flash memory cell. After irradiation, a threshold voltage shift of the flash memory cell is observed. The threshold voltages of a programmed cell and an erased cell are reduced at an average rate of 0.025 V/krad. The use of simulation techniques allows designers to better understand the TID response of a SST flash memory cell and to predict cell level TID effects without performing the costly in-situ irradiation experiments. The simulation and experimental results agree qualitatively. In particular, simulation results reveal that ‘0’ to ‘1’ errors but not ‘1’ to ‘0’ retention errors occur; likewise, ‘0’ to ‘1’ errors dominate experimental testing, which also includes circuitry effects that can cause ‘1’ to ‘0’ failures. Both simulation and experimental results reveal flash memory cell TID resilience to about 200 krad. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2016

La complexité des systèmes électroniques ne cesse d’augmenter, tout comme la tendance actuelle de miniaturisation des transistors. La fiabilité est ainsi devenue un continuel défi. Les environnements hostiles caractérisés par des conditions extrêmes de hautes températures affectent le bon fonctionnement des systèmes. Pour les composants de stockage de données, la température est considérée comme une menace pour la fiabilité. Le développement de techniques de suivi et de contrôle devient ainsi essentiel afin de garantir la fiabilité des mémoires volatiles et non volatiles. Dans le cadre de ma thèse, je me suis intéressée à deux types de mémoires : les mémoires NAND Flash et les mémoires SRAM. Pour contrôler les effets de la température sur les mémoires Flash, une solution basée sur l’utilisation d’un timer a été proposée afin de réduire la fréquence de rafraîchissement de ces mémoires tout en continuant à garantir l’intégrité de l’information stockée. Pour les mémoires SRAM, l’effet de la température sur la vulnérabilité par rapport aux événements singuliers (SEU) a été étudiée. Une étude comparative sur l’apparition des SEU a été menée avec différentes températures pour des cellules standards 6T-SRAM et des cellules de stockage durcies (DICE). Enfin, une méthode statistique et une approximation calculatoire basées sur des opérations de vérification périodique ont été proposées afin d’améliorer le taux d’erreurs (RBER) tolérable dans des SSDs de type Entreprise à base de mémoires Flash. / With the constant increase of microelectronic systems complexity and the continual scaling of transistors, reliability remains one of the main challenges. Harsh environments, with extreme conditions of high temperature and thermal cycling, alter the proper functioning of systems. For data storage devices, high temperature is considered as a main reliability threat. Therefore, it becomes essential to develop monitoring techniques to guarantee the reliability of volatile and non-volatile memories over an entire range of operating temperatures. In the frame of this thesis, I focus my studies on two types of memories: NAND Flash memories and SRAM. To monitor the effects of temperature in NAND Flash Memories, a timer-based solution is proposed in order to reduce the refresh frequency and continue to guarantee the integrity of data. For SRAM memories, the effect of temperature on Single Event Upset (SEU) sensitivity is studied. A comparative study on SEU occurrence under different temperatures is conducted for standard 6T-SRAM cells and hardened Dual Interlocked Storage Cells (DICE). Finally, statistical and computational approximation techniques based on periodic check operations are proposed in order to improve the tolerated Raw Bit Error Rate (RBER) in enterprise-class Flash based SSDs.