This thesis is composed of two parts: a high-speed transceiver front-end design with fault detection for FlexRay-based automative communication systems, and a temperature detector. In the first topic, a high-speed transceiver design with a fault detection circuit compliant with FlexRay standards V2.1 is proposed and realized on silicon. According to FlexRay physical layer standards, a LVDS-like transmitter is utilized to drive the twisted pair to generate a pair of differential signals. By contrast, a three-comparator-based receiver will recover the signals and then detect the mode of the bus. A failure detector is added at the transmitter to detect the operating current magnitude to avoid any over-current hazard. Meanwhile, a short-circuit detector is added at the receiver to detect short-circuit faults to vdd or gnd. The second topic discloses a temperature detector circuit, particularly dedicated for the reliability of any in-car system by sensing the temperature and the process at the same time. A discharging circuit composed of four PMOS transistors discharges until the output voltage is stable. It is composed of several reference voltages and comparators to determine the range of temperature and process. Eventually, by identifying the process corner and the temperature range, the reliability and safty of the car electrics will be ensured.

This thesis comprises two topics : the first one is the design and implementation of FlexRay automotive communication system physical layer. The second part is the design of a high efficiency DC/DC Buck converter with sub-3 ¡Ñ VDD. The first topic discloses the physical layer design comprising the Bus Guardian and the Bus Driver used in an in-vehicle network compliant with FlexRay standards. It is realized in a mixed-signal chip using TSMC 1P6M 0.18 £gm CMOS process. Its core area is less than 0.8 mm2, and power consumption is less than 60 mW. The second topic is to design a DC to DC step-down converter, which can accommodate wide range VDD. By utilizing stacked power MOSFETs, a voltage level converter, a detector and a controller, the design is realized by a typical 1P6M 0.18 £gm CMOS process without any high voltage technology. The core area is less than 0.184 mm2, while the VDD range is up to 5 V. Since the internal reference voltage is 1 V, it can increase the output regulation range. The proposed design attains very high conversion efficiency to prolong the life time of power supply. Therefore, it can be integrated in a system chip to provide multiple supply voltage sources.

Cette thèse revisite les algorithmes standards pour les problèmes d'accessibilité et de vivacité des automates temporisés. L'algorithme standard pour tester l'accessibilité consiste à utiliser l'inclusion de zones pour explorer efficacement un arbre de recherche abstrait. Cependant, l'ordre du parcours du graphe a une forte incidence sur l'efficacité de l'algorithme. Dans cette thèse nous introduisons deux stratégies, nommées ranking et waiting, et une combinaison des deux. De nombreux exemples montrent que la combinaison des deux stratégies aide l'algorithme d'accessibilité à éviter des explorations non nécessaires. Le problème de vivacité est couramment vérifiées par l'analyse des cycles dans l'automate temporisé. Contrairement à l'algorithme d'accessibilité, l'algorithme pour l'analyse de vivacité ne peut pas librement utiliser l'inclusion de zones. Par conséquent, il y a des situations où l'algorithme doit faire une longue exploration avant de conclure l'existence d'un cycle. Nous proposons une analyse accélérée des cycles, nommées w-iterability checking, qui permet d'améliorer la performance de l'algorithme de vivacité des automates temporisés. En plus, nous proposons une modélisation du mécanisme de démarrage du protocole FlexRay. La modélisation permet à vérifier le mécanisme dans configurations différents du réseau FlexRay. Nous présentons également un outil de visualisation qui aide à mieux comprendre le fonctionnement des algorithmes d'analyse. / This thesis revisits the standard algorithms for reachability and liveness analysis of timed automata. The standard algorithm for reachability analysis consists in using zone inclusion to efficiently explore a finite abstract zone graph of a timed automaton. It has been observed that the search order may strongly affect the performance of the algorithm. For the same algorithm, one search order may introduce a lot more exploration than another. In order to deal with the search order problem, we propose two strategies, named ranking strategy and waiting strategy, and a combination of the two. We show on a number of examples, the combining strategy helps to reduce unnecessary exploration in the standard algorithms. The standard algorithm for liveness analysis consists in looking for reachability of cycles in timed automata. But unlike the algorithm for safety analysis, the algorithm for liveness analysis cannot freely use zone inclusion. Consequently, there are situations where the algorithm has to perform a long exploration before reporting the result. In this thesis, we propose an accelerated checking for cycles in timed automata, named !-iterability checking, to improve the performance of the state-of-the-art algorithm for liveness analysis of timed automata. Furthermore, we present a new model for the startup procedure of FlexRay. The model allows to verify the procedure on different configurations of FlexRay networks. It also allows to evaluate the performance of our new strategies for safety analysis of timed automata. In addition, we present a methodology that uses visualization tools to get more insights into the execution of the algorithms.

V této práci je prezentován a popsán FlexRay komunikační protokol se sběrnicí. Je představeno několik matematických modelů vozidel pro simulaci a pro vývoj řídících systémů. Dále je popsána tvorba signálové brány pro testovací vozidlo. Software pro úpravu signálu je implementován a odzkoušen v testovacím vozidle. Matematick0 modely byli parametrizovány aby odpovídali skutečnému vozidlu. Vyvinuté řídící systémy pro ovládání vozidla skrze losí test byli implementovány do automobilu a jejich vlastnosti byli otestovány. Závěrem jsou prezentovány výsledky testů jednotlivých řídících systémů.

The growing amount and diversity of functions to be implemented by the current and future embedded applications (like, for example, in automotive electronics) have shown that, in many cases, time-triggered and event-triggered functions have to coexist on the computing nodes and to interact over the communication infrastructure. When time-triggered and event-triggered activities have to share the same processing node, a natural way for the execution support can be provided through a hierarchical scheduler. Similarly, when such heterogeneous applications are mapped over a distributed architecture, the communication infrastructure should allow for message exchange in both time-triggered and event-triggered manner in order to ensure a straightforward interconnection of heterogeneous components. This thesis studies aspects related to the analysis and design optimisation for safety-critical hard real-time applications running on hierarchically scheduled distributed embedded systems. It first provides the basis for the timing analysis of the activities in such a system, by carefully taking into consideration all the interferences that appear at run-time between the processes executed according to different scheduling policies. Moreover, due to the distributed nature of the architecture, message delays are also taken into consideration during the timing analysis. Once the schedulability analysis has been provided, the entire system can be optimised by adjusting its configuration parameters. In our work, the entire optimisation process is directed by the results from the timing analysis, with the goal that in the end the timing constraints of the application are satisfied. The analysis and design methodology proposed in the first part of the thesis is applied next on the particular category of distributed systems that use FlexRay as a communication protocol. We start by providing a schedulability analysis for messages transmitted over a FlexRay bus, and then by proposing a bus access optimisation algorithm that aims at improving the timing properties of the entire system. For all the problems that we investigated, we have carried out extensive experiments in order to measure the efficiency of the proposed solutions. The results have confirmed both the importance of the addressed aspects during system-level design, and the applicability of our techniques for analysing and optimising the studied systems.

The increasing use of electronic components in today&rsquo / s automobiles demands more powerful in-vehicle network communication protocols. FlexRay protocol, which is expected to be the de-facto standard in the near future, is a deterministic, fault tolerant and fast protocol designed for in vehicle communication. For proper operation of a FlexRay network the communication schedule needs to be computed and the nodes need to be configured before startup. Current software tools that are geared towards FlexRay only deal with the configuration process. The schedule needs to be computed by a network designer manually and it is necessary to input the designed schedule and the configurable parameters by hand. This thesis improves upon a previous scheduling software to automatically compute the network schedule, and then generate a universally acceptable FIBEX file that can be imported to available software tools to produce the necessary FlexRay node configuration files.

This thesis is composed of two critical circuit designs for FlexRay ECU (Electron-ics Control Unit), i.e., a transceiver with over-current protection, and a digital over-temperature protection circuit. Regarding the transceiver with over-current protection, to reduce the glitch prob-lem, we propose to use delay cells in the transmitter. In order to avoid the transmitter current which is higher than the upperbound defined by FlexRay specifications, we propose a current comparator circuit to detect the state where the transmitter should stop sending signals. The temperature protection is required for FlexRay specifications. We propose an over-temperature circuit in the thesis. By utilizing an oscillator-based structure, fre-quency to digital converter (FDC) circuit is developed as the core of the temperature protection mechanism. It will convert the frequency signal and output the sensed tem-perature in a digital code format. The output frequency at different process and temper-ature corners show a linear feature such that the range and accuracy of temperature de-tection is enhanced.

FlexRay is a new automotive network communication protocol for control and interconnection among ECUs (electronic control units) in the cluster. In the FlexRay protocol, a communication cycle consists of static segment and dynamic segment. The static segment is a TDMA scheme designed for transmitting time-triggered messages. Due to its determinism and reliability, it is particularly applicable to X-by-wire applications. Each static slot is allocated to a specified task and the task can transmit message during the exclusive slot. However, if the task has no message to transmit during its assigned slot, the slot cannot be used by other tasks. The overall utilization is low if the bandwidth requirement of each task is not high. To improve the system utilization, we apply the real-time scheduling techniques to devising a deterministic, static cyclic scheduling. The objective is to reduce the demand on the number of static slots needed for scheduling time-triggered tasks. Specifically, we treat the set of static slots that are in the same position in every communication cycle as an individual real-time channel. We model each task as a real-time task, specified by (Ci,Ti). It requires that for every Ti communication cycles, the system must allocate at least Ci time slots to satisfy the real-time constraint of the task. We decompose each such task into a set of subtasks, allocate them to the real-time channels and then apply the rate-monotonic scheduling algorithm to schedule the subtasks within each channel. Finally, we perform computer simulation to evaluate the effectiveness of our proposal. From the simulation results, we conclude that our proposal is able to effectively reduce the demand for the static slots under a wide range of real-time requirements.

The increasing use of electronic components in today&rsquo / s automobiles demands more powerful in-vehicle network communication protocols. FlexRay protocol, which is expected to be the de-facto standard in the near future, is a deterministic, fault tolerant and fast protocol designed for in vehicle communication. The current de-facto in-vehicle communication standard, CAN, and the future in-vehicle communication standard FlexRay will exist together in future cars. Data exchange between these two standards will be performed via Gateway units. In this thesis, end-to-end performance of a FlexRay-CAN network connected by a Gateway is evaluated as well as Gateway functionality and processing delay. The results of the experiments, which are performed for a realistic message set with various scheduling schemes, are presented and discussed.

FlexRay is a deterministic communication bus in the automotive context that supports fault-tolerant and high-speed bus system. It operates based on the time-division-multiple-access scheme and allows transmission of event-driven and time-driven messages between nodes in a system. A FlexRay bus has two periodic segments which form a bus cycle: static segment and dynamic segment. Such a bus system could be used in a wide area of real-time automotive applications with soft and hard timing constraints. Recent research has been focused on the FlexRay static segment. As opposed to the static segment, however, the dynamic one is based on an event-triggered scheme. This scheme is more difficult to be temporally predicted. Nevertheless, the event-triggered paradigm provides more flexibility for further incremental design. The dynamic segment is also suitable for applications with erratic data size. Such advantages motivate for more research on the dynamic segment. In a real-time system, results of the computations have to be ready by a specific instant of time called deadline . However, in a soft real-time application, the result can be used with a degraded Quality of Service even after the deadline has passed while in a hard real-time system, missing a deadline leads to a catastrophe. This thesis aims at optimizing some of the parameters of the FlexRay bus for soft real-time applications. The cost function which helps to assess the solution to the optimization problem is the deadline miss ratio and a solution to our problem consists of two parts: (1) Frame identifiers to messages which are produced at each node. (2) The size of each individual minislot which is one of the FlexRay bus parameters. The optimization is done based on genetic algorithms. To evaluate the proposed approach, several experiments have been conducted based on the FlexRay bus simulator implemented in this thesis. The achieved results show that suitable choice of the parameters which are generated by our optimization engine improves the timing behavior of simulated communicating nodes.