In February 2002, the FCC (2002 a, b) issued a ruling that ultra-wideband (UWB) could be used for data communications as well as for radar and safety applications. UWB system is constrained to have a maximum power transmission of -41 dBm and a bandwidth ranging from 3.1-10.6 GHz. UWB co-exists and does not interfere with the existing narrowband or wideband communication systems in the same spectrum. However, due to its low power in the same bandwidth, UWB is affected by the so-called narrowband (NB) interference. This thesis presents a method to estimate and detect narrowband signals in radio impulse receiver with the intention to eliminate the NB interference. <p>Narrowband bandwidth is very small compared to the bandwidth of UWB therefore the interference can be considered as a single tone. To detect such a tone using conventional techniques is not feasible at least up to this time for UWB as current technology can not support such high data rates. Alternatives way to track down the narrowband signal include using a power spectral density estimation technique called spectrogram. For all cases, the spectrogram at specific frequency range where the narrowband active statistically be larger than its overall average power. Here, a threshold detector is built which reports detection at the frequency range where the narrowband is located if the spectrogram exceeds a threshold value. <p>Upon completing of successful NB detection, the NB signal in the UWB system will be estimated in digital form and cancelled in analog form. The pipelined LMS algorithm is used to estimate the NB signal; the algorithm is implemented using a built-in IP core from the Altera DSP library which can be simulated in either Matlab platform or in FPGA boards. The design correctness has been validated by means of Monte-Carlo simulation and hardware implementation using standard UWB IEEE standard channel models, Time Hopping-Pulse Position Modulation and the rake receiver technique.

The ease with which indoor wireless systems can be installed has become their main selling feature. A desirable application for wireless systems is the transmission of compressed digital music in an indoor shopping mall environment. The indoor environment, with its many walls and highly reflective surfaces, has a high level of multipath. High levels of slowly changing multipath can cause deep fades, and therefore reduce the reliability of the system. <p> The proper use of multiple receiving elements is one way to mitigate the deep fades caused by multipath. The main objective of this thesis is to study a simple and cost effective approach to combining the signals from several receiving elements. A novel diversity combining approach using 2 receiving elements is presented. The novel diversity combining approach consists of periodically changing the phase of one of the two received signals. <p> A set of simulations was developed to study the effectiveness of the novel diversity combining method in mitigating deep multipath fades. The relative performances of two different implementations of the diversity combining were compared to a baseline test case that did not include diversity combining. In both of the simulated implementations, the diversity combining approach proved to be an effective means of mitigating the multipath fading phenomenon. <p> A proof-of-concept, bench-top hardware prototype was also developed. The transmitter and receiver were implemented in Field Programmable Gate Arrays (FPGAs). The laboratory testing of the hardware successfully illustrated the feasibility of the proof-of-concept system.

The ease with which indoor wireless systems can be installed has become their main selling feature. A desirable application for wireless systems is the transmission of compressed digital music in an indoor shopping mall environment. The indoor environment, with its many walls and highly reflective surfaces, has a high level of multipath. High levels of slowly changing multipath can cause deep fades, and therefore reduce the reliability of the system. <p> The proper use of multiple receiving elements is one way to mitigate the deep fades caused by multipath. The main objective of this thesis is to study a simple and cost effective approach to combining the signals from several receiving elements. A novel diversity combining approach using 2 receiving elements is presented. The novel diversity combining approach consists of periodically changing the phase of one of the two received signals. <p> A set of simulations was developed to study the effectiveness of the novel diversity combining method in mitigating deep multipath fades. The relative performances of two different implementations of the diversity combining were compared to a baseline test case that did not include diversity combining. In both of the simulated implementations, the diversity combining approach proved to be an effective means of mitigating the multipath fading phenomenon. <p> A proof-of-concept, bench-top hardware prototype was also developed. The transmitter and receiver were implemented in Field Programmable Gate Arrays (FPGAs). The laboratory testing of the hardware successfully illustrated the feasibility of the proof-of-concept system.

Difficulties and dangers in doing experiments on living systems and providing a testbed for theorists make the biologically detailed neural simulation an essential part of neurobiology. Due to the complexity of the neural systems and dynamic properties of the neurons simulation of biologically realistic models is very challenging area. Currently all general purpose simulator are software based. Limitation on the available processing power provides a huge gap between the maximum practical simulation size and human brain simulation as the most complex neural system. This thesis aimed at providing a hardware friendly parallel architecture in order to accelerate the simulation process.<p> This thesis presents a scalable hierarchical architecture for accelerating simulations of large-scale biological neural systems on field-programmable gate arrays (FPGAs). The architecture provides a high degree of flexibility to optimize the parallelization ratio based on available hardware resources and model specifications such as complexity of dendritic trees. The whole design is based on three types of customized processors and a switching module. An addressing scheme is developed which allows flexible integration of various combination of processors. The proposed addressing scheme, design modularity and data process localization allow the whole system to extend over multiple FPGA platforms to simulate a very large biological neural system.<p> In this research Hodgkin-Huxley model is adopted for cell excitability. Passive compartmental approach is used to model dendritic tree with any level of complexity. The whole architecture is verified in MATLAB and all processor modules and the switching unit implemented in Verilog HDL and Schematic Capture. A prototype simulator is integrated and synthesized for Xilinx V5-330t-1 as the target FPGA. While not dependent on particular IP (Intellectual Property) cores, the whole implementation is based on Xilinx IP cores including IEEE-754 64-bit floating-point adder and multiplier cores. The synthesize results and performance analyses are provided.

A physical control/protection platform needs to be tested and its functionality verified prior to installation and commissioning. Closed-loop testing of a physical control/protection platform, in a real-time simulator environment is practically the only option to safely and thoroughly verify the design integrity and evaluate its functionality and performance. Moreover, a real-time simulator is also required to conduct statistical switching studies, as it substantially reduces the total run time of the study. This thesis proposes and develops a generalized methodology for implementation of the power system equations in the FPGA environment. The developed methodology enables real-time operation, for closed-loop testing of physical control/protection platforms in hardware-in-the-loop (HIL) configuration, and even faster-than-real-time operation, for statistical switching studies. Based on the developed methodology, an FPGA-based simulator is developed and tested. The salient features of the proposed implementation are: ² It enables the use of a nanosecond range simulation time-step to simulate large systems in real-time, in contrast to the us range time-steps used in the existing simulators. Thus it is also able to provide a wide frequency bandwidth for the simulation results. ² It retains the calculation time, within each simulation time-step, nearly fixed irrespective of the size of the system. ² It eliminates the need for the corrective measures, adopted in the existing real-time simulators, to reduce error due to the lack of synchronization between the simulation time-grid and the output signals of the control/protection platform under test. As an integral part of this work, this thesis proposes and develops the modified two-layer network equivalent (M-TLNE). The salient feature of the M-TLNE is its computational efficiency, as compared to the existing network equivalents, which makes it a prime choice for statistical switching studies and real-time simulation of electromagnetic transients. This thesis also proposes a generalized methodology, applicable to both single and multi-port network equivalents for both single- and multi-phase systems, for developing the proposed M-TLNE. The developed methodology ensures the stability and passivity of the M-TLNE.

Field Programmable Gate Arrays (FPGA) are increasingly being used to design high end computationally intense microprocessors capable of handling both fixed and floating-point mathematical operations. Addition is the most complex operation in a floating-point unit and offers major delay while taking significant area. Over the years, the VLSI community has developed many floating-point adder algorithms mainly aimed to reduce the overall latency. An efficient design of floating-point adder onto an FPGA offers major area and performance overheads. With the recent advancement in FPGA architecture and area density, latency has been the main focus of attention in order to improve performance. Our research was oriented towards studying and implementing standard, Leading One Predictor (LOP), and far and close data-path floating-point addition algorithms. Each algorithm has complex sub-operations which lead significantly to overall latency of the design. Each of the sub-operation is researched for different implementations and then synthesized onto a Xilinx Virtex2p FPGA device to be chosen for best performance. This thesis discusses in detail the best possible FPGA implementation for all the three algorithms and will act as an important design resource. The performance criterion is latency in all the cases. The algorithms are compared for overall latency, area, and levels of logic and analyzed specifically for Virtex2p architecture, one of the latest FPGA architectures provided by Xilinx. According to our results standard algorithm is the best implementation with respect to area but has overall large latency of 27.059 ns while occupying 541 slices. LOP algorithm improves latency by 6.5% on added expense of 38% area compared to standard algorithm. Far and close data-path implementation shows 19% improvement in latency on added expense of 88% in area compared to standard algorithm. The results clearly show that for area efficient design standard algorithm is the best choice but for designs where latency is the criteria of performance far and close data-path is the best alternative. The standard and LOP algorithms were pipelined into five stages and compared with the Xilinx Intellectual Property. The pipelined LOP gives 22% better clock speed on an added expense of 15% area when compared to Xilinx Intellectual Property and thus a better choice for higher throughput applications. Test benches were also developed to test these algorithms both in simulation and hardware. Our work is an important design resource for development of floating-point adder hardware on FPGAs. All sub components within the floating-point adder and known algorithms are researched and implemented to provide versatility and flexibility to designers as an alternative to intellectual property where they have no control over the design. The VHDL code is open source and can be used by designers with proper reference.

Architectural research for Field-Programmable Gate Arrays (FPGAs) tends to use an experimental approach. The benchmark circuits are used not only to compare different architectures, but also to ensure that the FPGA is sufficiently flexible to implement the desired variety of circuits. The most common benchmark circuits used for architectural research are circuits from the Microelectronics Center of North Carolina (MCNC). These circuits are small; they occupy less than 3% [5] of the largest available commercial FPGA. Moreover, these circuits are more representative of the glue logic circuits that were targets of early devices. This contrasts with the trend towards implementing Systems on Chip (SoCs) on FPGAs where several functional modules are integrated into a single circuit which is mapped onto one device. In this thesis, we develop a synthetic system-level circuit generator that connects pre-existing circuits in a realistic manner to build large netlists that share the characteristics of real SoC circuits. This generator is based on a survey of contemporary circuit designs from industrial and academic sources. We demonstrate that these system-level circuits scale well and that their post-routing characteristics match the results of large pre-existing benchmarks better than the results of circuits from previous synthetic generators.

Vid implementering av realtidsapplikationer krävs det att man kan använda hårdvaran på ett deterministiskt vis. En realtidsapplikation ställer stora krav på körtider och hur applikationen schemaläggs. Det är därför av största vikt att kontrollera om de uppfyller dessa krav. I detta examensarbete har tre system för realtidsapplikationer jämförts och en analys av framförallt sina beräkningsförmågor och hur pass deterministiskt de uppför sig gällande körtider har gjorts. Även andra aspekter så som utvecklingsmiljöer för mjukvara, tillbehör och effektförbrukning har jämförts.

This report describes the development and implementation of a system for transmitting digital information at high speeds from a miniaturized submersible developed by the Ångström Space Technology Centre at Uppsala University. For instance, the vehicle shall transmit image data – even stream live video - through an optical fibre to a monitor in a ground station. Hence, the system shall be used both to convert the image data to make it transmittable, and to recreate it at the receiver. The work includes a pre-study of the programming language and the technology used. A concept for the solution is presented together with main components later broken down into internal functions. Following on this, other components that were necessary for fulfilling the function of the main components were identified. The system was developed with the hardware description language VHDL in order to be implementable and testable on an FPGA platform, but also to be transferable to other devices. After the development and implementation on the hardware platform, the system was tested and verified. Analysis showed that some modifications were required to produce the desired results. These modifications implied some deviations from the assignment statement but gave rise to suggestions for further improvement of the concept. All in all, however, the solution was successfully verified since the transmitted data was possible to recreate the original image. The report contains drawings of the developed system and the source code it consists of. / Deeper Access, Deeper Understanding

This paper presents a reconfigurable FFT architecture for variable length andmultistreaming WiMax wireless standard. The architecture processes 1 streamof 2048-pt FFT, up to 2 streams of 1024-pt FFT or up to 4 streams of 512-ptFFT. The architecture consists of 11 SDF pipelined stages and radix-2 butterflyis calculated in each stage. The sampling frequency of the system is varied inaccordance with FFT length. The wordlength and buffer length in each stage isconfigurable depending on the FFT length. Latch-free clock gating technique isused to reduce power consumption.The architecture is synthesized for Virtex-6 XCVLX760 FPGA. Experimentalresults show that the architecture achieves the throughput as required by theWiMax standard and the design has additional features compared to the previousapproaches. The design used 1% of the total available FPGA resources andmaximum clock frequency of 313.67 MHz was achieved.