archives@tulane.edu / The fundamental problem of thermalization in quantum systems with long-range interactions is a target of the present study. This problem is relevant for the vast number of phenomena ranging from thermal conductivity of materials to error propagation in quantum computers. Two types of quantum systems are studied analytically in this work with a support from numerical simulations. Spin chains with power-law interactions are chosen as an example system that represents behavior of qubits in a quantum computer while the vibrational problem with non-linear interactions is a toy model of a polymer molecule with anharmonic bonding. The analytical results developed for both models within the framework of resonant counting method allow one to predict the integrability-chaos transitions for the future experimental verification. / 1 / Andrii Makysmov

<p>In this master thesis, the possibilities of customizing a low-cost microprocessor with the purpose of replacing an existing microprocessor solution are investigated. A brief survey of suitable processors is carried out wherein a replacement is chosen. The replacement processor is then analyzed and extended with accelerators in order to match set requirements.</p><p>The result is a port of the processor Lattice Mico32 for the FPGA curcuit Xilinx Virtex-5 which replaces an earlier solution using Xilinx MicroBlaze. To reach the set requirements, accelerators for floating point arithmetics and FIR filtering have been developed. The toolchain for the processor has been modified to support the addition of accelerated floating point arithmetics.</p><p>A final evaluation of the presented solution shows that it fulfills the set requirements and constitutes a functional replacement for the previous solution.</p>

While Application Specific Instruction Set Processors (ASIPs) have allowed designers to create processors with custom instructions to target specific applications, floating-point units (FPUs) are still instantiated as non-customizable general-purpose units, which if under utilized, wastes area and performance. However, customizing FPUs manually is a complex and time-consuming process. Therefore, there is a need for an automated custom FPU generation scheme. This thesis presents a methodology for generating application-specific FPUs customized at the instruction level, with integrated datapath merging to minimize area. The methodology reduces the subset of floating-point instructions implemented to the minimum required for the application. Datapath merging is then performed on the required datapaths to minimize area. Previous datapath merging techniques failed to consider merging components of different bit-widths and thus ignore the bit-alignment problem in datapath merging. This thesis presents a novel bit-alignment solution during datapath merging. In creating the custom FPU, the subset of floating-point instructions that should be implemented in hardware has to be determined. Implementing more instructions in hardware reduces the cycle count of the application, but may lead to increased delay due to multiplexers inserted on the critical path during datapath merging. A rapid design space exploration was performed to explore the trade-offs. By performing this exploration, a designer could determine the number of instructions that should be implemented as a custom FPU and the number that should be left for software emulation, such that performance and area meets the designer's requirements. Customized FPUs were generated for different Mediabench applications and compared to a fully-featured reference FPU that implemented all floating-point operations. Reducing the floating-point instruction set reduced the FPU area by an average of 55%. Performing instruction reduction and then datapath merging reduced the FPU area by an average of 68%. Experiments showed that datapath merging without bit-alignment achieved an average area reduction of 10.1%. With bit-alignment, an average of 16.5% was achieved. Bit-alignment proved most beneficial when there was a diverse mix of different bit-widths in the datapaths. Performance of Field-Programmable Gate Arrays (FPGAs) used for floating-point applications is poor due to the complexity of floating-point arithmetic. Implementing floating-point units on FPGAs consume a large amount of resources. Therefore, there is a need for embedded FPUs in FPGAs. However, if unutilized, they waste area on the FPGA die. To overcome this issue, a novel flexible multi-mode embedded FPU for FPGAs is presented in this thesis that can be configured to perform a wide range of operations. The floating-point adder and multiplier in the embedded FPU can each be configured to perform one double-precision operation or two single-precision operations in parallel. To increase flexibility further, access to the large integer multiplier, adder and shifters in the FPU is provided. It is also capable of floating-point and integer multiply-add operations. Benchmark circuits were implemented on both a standard Xilinx Virtex-II FPGA and on the FPGA with embedded FPU blocks. The implementations on the FPGA with embedded FPUs showed mean area and delay improvements of 5.2x and 5.8x respectively for the double-precision benchmarks, and 4.4x and 4.2x for the single-precision benchmarks.

While Application Specific Instruction Set Processors (ASIPs) have allowed designers to create processors with custom instructions to target specific applications, floating-point units (FPUs) are still instantiated as non-customizable general-purpose units, which if under utilized, wastes area and performance. However, customizing FPUs manually is a complex and time-consuming process. Therefore, there is a need for an automated custom FPU generation scheme. This thesis presents a methodology for generating application-specific FPUs customized at the instruction level, with integrated datapath merging to minimize area. The methodology reduces the subset of floating-point instructions implemented to the minimum required for the application. Datapath merging is then performed on the required datapaths to minimize area. Previous datapath merging techniques failed to consider merging components of different bit-widths and thus ignore the bit-alignment problem in datapath merging. This thesis presents a novel bit-alignment solution during datapath merging. In creating the custom FPU, the subset of floating-point instructions that should be implemented in hardware has to be determined. Implementing more instructions in hardware reduces the cycle count of the application, but may lead to increased delay due to multiplexers inserted on the critical path during datapath merging. A rapid design space exploration was performed to explore the trade-offs. By performing this exploration, a designer could determine the number of instructions that should be implemented as a custom FPU and the number that should be left for software emulation, such that performance and area meets the designer's requirements. Customized FPUs were generated for different Mediabench applications and compared to a fully-featured reference FPU that implemented all floating-point operations. Reducing the floating-point instruction set reduced the FPU area by an average of 55%. Performing instruction reduction and then datapath merging reduced the FPU area by an average of 68%. Experiments showed that datapath merging without bit-alignment achieved an average area reduction of 10.1%. With bit-alignment, an average of 16.5% was achieved. Bit-alignment proved most beneficial when there was a diverse mix of different bit-widths in the datapaths. Performance of Field-Programmable Gate Arrays (FPGAs) used for floating-point applications is poor due to the complexity of floating-point arithmetic. Implementing floating-point units on FPGAs consume a large amount of resources. Therefore, there is a need for embedded FPUs in FPGAs. However, if unutilized, they waste area on the FPGA die. To overcome this issue, a novel flexible multi-mode embedded FPU for FPGAs is presented in this thesis that can be configured to perform a wide range of operations. The floating-point adder and multiplier in the embedded FPU can each be configured to perform one double-precision operation or two single-precision operations in parallel. To increase flexibility further, access to the large integer multiplier, adder and shifters in the FPU is provided. It is also capable of floating-point and integer multiply-add operations. Benchmark circuits were implemented on both a standard Xilinx Virtex-II FPGA and on the FPGA with embedded FPU blocks. The implementations on the FPGA with embedded FPUs showed mean area and delay improvements of 5.2x and 5.8x respectively for the double-precision benchmarks, and 4.4x and 4.2x for the single-precision benchmarks.

This thesis implemented a field programmable gate array (FPGA)-based face detector using a neural network (NN), as well as a bit-width reduced floating-point unit (FPU). An NN was used to easily separate face data and non-face data in the face detector. The NN performs time consuming repetitive calculation. This time consuming problem was solved by a Field Programmable Gate Array (FPGA) device and a bit-width reduced FPU in this thesis. A floating-point bit-width reduction provided a significant saving of hardware resources, such as area and power.<p>The analytical error model, using the maximum relative representation error (MRRE) and the average relative representation error (ARRE), was developed to obtain the maximum and average output errors for the bit-width reduced FPUs. After the development of the analytical error model, the bit-width reduced FPUs and an NN were designed using MATLAB and VHDL. Finally, the analytical (MATLAB) results, along with the experimental (VHDL) results, were compared. The analytical results and the experimental results showed conformity of shape. It was also found that while maintaining 94.1% detection accuracy, a reduction in bit-width from 32 bits to 16 bits reduced the size of memory and arithmetic units by 50%, and the total power consumption by 14.7%.

In this master thesis, the possibilities of customizing a low-cost microprocessor with the purpose of replacing an existing microprocessor solution are investigated. A brief survey of suitable processors is carried out wherein a replacement is chosen. The replacement processor is then analyzed and extended with accelerators in order to match set requirements. The result is a port of the processor Lattice Mico32 for the FPGA curcuit Xilinx Virtex-5 which replaces an earlier solution using Xilinx MicroBlaze. To reach the set requirements, accelerators for floating point arithmetics and FIR filtering have been developed. The toolchain for the processor has been modified to support the addition of accelerated floating point arithmetics. A final evaluation of the presented solution shows that it fulfills the set requirements and constitutes a functional replacement for the previous solution.

This thesis implemented a field programmable gate array (FPGA)-based face detector using a neural network (NN), as well as a bit-width reduced floating-point unit (FPU). An NN was used to easily separate face data and non-face data in the face detector. The NN performs time consuming repetitive calculation. This time consuming problem was solved by a Field Programmable Gate Array (FPGA) device and a bit-width reduced FPU in this thesis. A floating-point bit-width reduction provided a significant saving of hardware resources, such as area and power.<p>The analytical error model, using the maximum relative representation error (MRRE) and the average relative representation error (ARRE), was developed to obtain the maximum and average output errors for the bit-width reduced FPUs. After the development of the analytical error model, the bit-width reduced FPUs and an NN were designed using MATLAB and VHDL. Finally, the analytical (MATLAB) results, along with the experimental (VHDL) results, were compared. The analytical results and the experimental results showed conformity of shape. It was also found that while maintaining 94.1% detection accuracy, a reduction in bit-width from 32 bits to 16 bits reduced the size of memory and arithmetic units by 50%, and the total power consumption by 14.7%.

Dissertação(mestrado) - Universidade Federal do Rio Grande, Programa de Pós-Graduação em Engenharia Oceânica, Escola de Engenharia, 2010. / Submitted by Lilian M. Silva (lilianmadeirasilva@hotmail.com) on 2013-04-23T00:25:38Z No. of bitstreams: 1 Monitoramento de Deformações e Deslocamentos Relativos nas Estruturas de Suporte de Plantas de Processo Modulares em Unidades Flutuantes de Produção de Petróleo do Tipo FPSO.pdf: 3764587 bytes, checksum: 70312a121e0f141c7936b32ac56e47c2 (MD5) / Approved for entry into archive by Bruna Vieira(bruninha_vieira@ibest.com.br) on 2013-06-03T19:38:06Z (GMT) No. of bitstreams: 1 Monitoramento de Deformações e Deslocamentos Relativos nas Estruturas de Suporte de Plantas de Processo Modulares em Unidades Flutuantes de Produção de Petróleo do Tipo FPSO.pdf: 3764587 bytes, checksum: 70312a121e0f141c7936b32ac56e47c2 (MD5) / Made available in DSpace on 2013-06-03T19:38:06Z (GMT). No. of bitstreams: 1 Monitoramento de Deformações e Deslocamentos Relativos nas Estruturas de Suporte de Plantas de Processo Modulares em Unidades Flutuantes de Produção de Petróleo do Tipo FPSO.pdf: 3764587 bytes, checksum: 70312a121e0f141c7936b32ac56e47c2 (MD5) Previous issue date: 2010 / Os projetos mais recentes de plataformas do tipo FPSO da PETROBRAS utilizam plantas modulares sobre cascos convertidos de mais de 300m de comprimento. Os módulos podem atingir 2.000t (peso seco) e mais de 3.000t em operação, sendo suportados em quatro pontos por estruturas chamadas stools. No projeto da P-53, para cada módulo há dois stools deslizantes (os quais permitem deslocamentos longitudinais, paralelos ao eixo da embarcação), e dois fixos (com restrição de movimentos em todas as direções), cada par em transversais distintas. Teoricamente, os stools deslizantes são empregados para evitar que os efeitos das deflexões do casco da plataforma induzam esforços nas estruturas dos módulos. As dúvidas a respeito da eficiência deste mecanismo para essa configuração de suportação de módulos motivaram a realização deste trabalho, cujo objetivo é analisar e compreender o comportamento estrutural dos apoios dos módulos (stools) da plataforma P-53. Para se obter estas respostas, foi desenvolvido um projeto de pesquisa na FURG com apoio da PETROBRAS, o qual mobilizou três pesquisadores e dez bolsistas, durante 3 anos e meio. Um sistema de aquisição de dados foi especialmente implementado, e através deste foram monitoradas deformações e deslocamentos relativos sobre esses stools. No total foram instalados na plataforma 75 sensores (entre extensômetros, transdutores de deslocamento e acelerômetros). Foram realizadas medições durante o assentamento dos módulos sobre a embarcação ainda no estaleiro, e na locação final, submetida às condições ambientais da Bacia de Campos. Nas condições em que foi realizado o monitoramento, não foram registrados deslocamentos relativos entre os stools deslizantes e os pés dos módulos durante todo o período de observação. A não ocorrência de deslizamento pode ser justificada pelo elevado peso dos módulos, alto coeficiente de atrito, e as características das ondas sob as quais a embarcação foi submetida. Nestas condições, a ocorrência de deslocamentos relativos é mais provável para módulos mais leves, e improvável, ou até impossível, para módulos mais pesados. Mesmo assim não foram registrados níveis de deformações que pudessem indicar um incremento relevante de carga sobre as estruturas dos stools e dos módulos. / The most recent PETROBRAS FPSO projects used modular process plants on converted vessels with more than 300m length. The modules may reach 2,000t (dry) and more than 3,000t on operation, being supported by four points on structures called stools. In the P-53 design, there are two sliding stools (that allow longitudinal displacements, parallel to vessel axis), and two fixed stools (that restrict the displacement in all directions), each pair is at different transversal frames on the hull. In theory, the sliding stools are employed to avoid that the hull deflections induce deformation on the module’s structures. The doubts about the efficiency of this apparatus for this support configuration of modules motivated the development of this research, which aim is analyze and understand the structural behavior of the module’s supports. To get these answers, it was developed a research in FURG with support of PETROBRAS, which mobilized three researchers and ten students, during three and a half year. A data acquisition system was specially implemented to attend this goal, through that was monitored strain and relative displacements on these stools. A total of 75 sensors (among them strain gages, displacement transducer and accelerometers) was installed on the platform. It was taken measurements during the installation of the modules upon the hull at the shipyard, and at the final location, under the environmental conditions of Campos Basin. In these conditions where the monitoring was done, no relative displacement among the sliding stools and module’s pads was recorded throughout the observation period. The non-occurrence of sliding can be justified by the high weight of the modules and high coefficient of friction, and by the environmental conditions under that the vessel was subjected. On these conditions, the occurrence of relative displacements is more probable to lighter modules, and improbable, even impossible to heavier ones. Despite that, it was not recorded strain levels that could indicate a relevant load increasing on the structures of modules or stools.

Le nombre de transistors dans une puce augmente constamment en suivant la conjecture de Moore, qui dit que le nombre de transistors dans une puce double tous les 2 ans. On arrive donc aujourd’hui à des systèmes d’une telle complexité que l’exploration architecturale ou le développement, même parallèle, de la conception de la puce et du code applicatif prend trop de temps. Pour réduire ce temps, la solution généralement admise consiste à développer des plateformes virtuelles reproduisant le comportement de la puce cible. Avoir une haute vitesse de simulation est essentiel pour ces plateformes, notamment pour les systèmes many-cœurs à cause du grand nombre de cœurs à simuler. Nous nous focalisons donc dans cette thèse sur la simulation native, dont le principe est de compiler le code source directement pour l’architecture hôte, offrant ainsi un temps de simulation que l’on peut espérer optimal. Mais un certain nombre de caractéristiques fonctionnelles spécifiques au cœur cible peuvent ne pas être présentes sur le cœur hôte. L’utilisation de l’assistance matérielle à la virtualisation (HAV) comme base pour la simulation native vient renforcer la dépendance de la simulation du cœur cible par rapport aux caractéristiques du cœur hôte. Nous proposons dans ce contexte un moyen de simuler les caractéristiques fonctionnelles spécifiques du cœur cible en simulation native basée sur le HAV. Parmi les caractéristiques propres au cœur cible, l’unité de calcul à virgule flottante est un élément important, bien trop souvent négligé en simulation native conduisant certains calculs à donner des résultats différents entre le cœur cible et le cœur hôte. Nous nous restreignons au cas de la simulation compilée et nous proposons une méthodologie permettant de simuler correctement les opérations de calcul à virgule flottante. Finalement la simulation native pose des problèmes de passage à l’échelle. Des problèmes de découplage temporel amènent à simuler inutilement certaines instructions lors de procédures de synchronisation entre des tâches s’exécutant sur les cœurs cibles, conduisant à une réduction de la vitesse de simulation. Nous proposons des solutions pour permettre un meilleur passage à l’échelle de la simulation native. / The number of transistors in one chip is increasing following Moore’s conjecture which says that the number of transistors per chip doubles every two years. Current systems are so complex that chip design and specific software development for one chip take too much time even if software development is done in parallel with the design of the hardware architecture, often because of system integration issues. To help reducing this time, the general solution consists of using virtual platforms to reproduce the behavior of the target chip. The simulation speed of these platforms is a major issue, especially for many-core systems in which the number of programmable cores is really high. We focus in this thesis on native simulation. Its principle is to compile source code directly for the host architecture to allow very fast simulation, at the cost of requiring "equivalent" features on the target and host cores.However, some target core specific features can be missing in the host core. Hardware Assisted Virtualization (HAV) is used to ease native simulation but it reinforces the dependency of the target chip simulation regarding the host core capabilities. In this context, we propose a solution to simulate the target core functional specific features with HAV based native simulation.Among target core features, the floating point unit is an important element which is neglected in native simulation leading to potential functional differences between target and host computation results. We restrict our study to the compiled simulation technique and we propose a methodology ensuring to accurately simulate floating point computations while still keeping a good simulation speed.Finally, native simulation has a scalability issue. Time decoupling problems generate unnecessary code simulation during synchronisation protocols between threads executed on the target cores, leading to an important decrease of simulation speed when the number of cores grows. We address this problem and propose solutions to allow a better scalability for native simulation.

Afin de mettre en évidence le phénomène de localisation d'énergie dans les protéines, un modèle utilisant les concepts de la Physique non-linéaire a été développé. Il permet, via l'utilisation d'un potentiel de type FPU et d'une dissipation placée sur la surface, de faire apparaître des breathers chaotiques dans certaines enzymes. Ces breathers ont une durée de vie importante par rapport aux échelles de temps caractéristiques du système. Ils sont localisés sur un seul résidu, toujours situé dans une région rigide de la protéine. Cela nous a conduit à l'hypothèse d'un lien possible entre la fonction catalytique, les propriétés locales de structure des enzymes et les localisations d'énergie. Plus précisément, l'activation d'un breather chaotique lors d'une réaction enzymatique au niveau des sites catalytiques pourrait permettre à la protéine de stocker de l'énergie pendant de longues durées.