University, Diss., 2003--Saarbrücken.

Dose as a result of radiation exposure is the notion generally used to disclose the imparted energy in a volume of tissue to a potential biological effect. The basic unit defined by the international system of units (SI system) is the radiation absorbed dose, which is expressed as the mean imparted energy in a mass element of the tissue known as "gray" (Gy) or J/kg. The procedure for ascertaining the absorbed dose is complicated since it involves the radiation transport of numerous types of charged particles and coupled photon interactions. The most precise method is to perform a full 3D Monte Carlo simulation of the radiation transport. There are various Monte Carlo toolkits that have tool compartments for dose calculations and measurements. The dose studies in this thesis were performed using the GEANT4 Application for Emission Tomography (GATE) software (Janet al., 2011) GATE simulation toolkit has been used extensively in the medical imaging community, due to the fact that it uses the full capabilities of GEANT4. It also utilizes an easy to-learn GATE macro language, which is more accessible than learning the GEANT4/C++ programming language. This work combines GATE with digital phantoms generated using the NCAT (NURBS-based cardiac-torso phantom) toolkit (Segars et al., 2004) to allow efficient and effective estimation of 3D radiation dose maps. The GATE simulation tool has developed into a beneficial tool for Monte Carlo simulations involving both radiotherapy and imaging experiments. This work will present an overview of absorbed dose of common radionuclides used in nuclear medicine and serve as a guide to a user who is setting up a GATE simulation for a PET and SPECT study.

A new, and thus far only, method to overcome a selectivity barrier in parametrically pumped quantum pulse gates is proposed and experimentally demonstrated for the first time, using frequency conversion of optical temporal modes in second-order nonlinear waveguides. Temporal modes and quantum pulse gates are defined and their utilities are explored. Pulsed operation of three-field and four-field, parametric, optical processes are modeled and numerically investigated. A maximum limit to achievable selectivity for quantum pulse gating in uniform media is discovered and theoretically explained. An interferometric means of overcoming said limit and asymptotically approaching unit selectivity is proposed. The principle is experimentally verified by double-passing specifically shaped optical pulses derived from an ultrafast Ti:sapphire laser through a periodically-poled lithium niobate waveguide phasematched for sum-frequency generation. Further improvements and future implications for quantum technologies are discussed.

A systematic approach has been used to optimise the fabrication process of pentacene-based nonvolatile organic thin film memory transistors (OTFMTs) operating at low programming voltages. In the first part of this work, reliable, reproducible and hysteresis free organic metal-insulator-semiconductor (OMIS) devices and organic thin film transistors (OTFTs) were fabricated and characterised. All devices were based on poly(methyl methacrylate) (PMMA) and poly(vinyl phenol) (PVP) as the organic insulators. The second part of this work focused on optimising the evaporation parameters to fabricate high-performance pentacene-based devices. About 50 nm thickness of pentacene film with a deposition rate of 0.03 nm s-1 on ~ 300 nm of PMMA was found to produce large, uniform and condense grains leading to high quality devices. OTFTs with high mobility of 1.32 cm2 V−1 s−1, on/off current ratio of 106, and negligible hysteresis and leakage current were demonstrated. The effect of the environment on the OTFTs obehaviour was also investigated. The bias stress effect was also investigated in terms of threshold voltage shift ΔVT at various conditions and times. The results show ΔVT increases with the increase of stress voltage. A negligible hysteresis is evident between the forward and reverse direction of the transfer characteristics and the shape of the transfer characteristics does not change with the bias stress. Floating gate memory structures with thin layer of gold, gold nanoparticles (AuNPs) and single walled carbon nanotubes (SWCNTs) were fabricated and characterised during this investigation. Hysteresis in memory structures was a clear indication of the memory effect and charge storage in these devices. Also, the hysteresis was centred close to 0 V for SWCNTs-based structures, which indicate that a low operation voltage is needed to charge the devices. A memory window of about 40 V was observed for AuNPs-based memory devices based on PVP; while the memory windows for devices based on PMMA with thin layer of Au and AuNPs floating gates were 22 V and 32 V, respectively. The electrical properties of the OTFMTs were improved by the use of the Au nanoparticles as the floating gate compared with that of an Au thin film. Using appropriate negative or positive voltages, the floating gate was charged and discharged, resulting in a clear shift in the threshold voltage of the memory transistors. Negative and positive pulses of 1 V resulted in clear write and erase states, respectively. Additionally, these organic memory transistors exhibited rather high carrier mobility of about μ = 0.319 cm2 V-1 s-1. Furthermore the data retention and endurance measurements confirmed the non-volatile memory properties of the memory devices fabricated in this study.

[pt] Programas de computador já vem sendo utilizados há muito tempo no projeto de circuitos integrados, principalmente para verificação e simulação. Os anos 80 viram surgir os compiladores de silício, novas ferramentas para a geração automática de estruturas e leiautes. O sistema apresentado nesse trabalho permite a geração automática do leiaute de uma via de dados (conjunto de registradores e ALUs) a partir de uma descrição de seu tamanho e componentes. É também apresentado um gerador de leiautes gate matrix com facilidades para posicionamento de terminais, utilizando para a criação das células da biblioteca do gerador de vias. São discutidos também os problemas envolvidos nas diversas etapas de geração, assim como as soluções encontradas. / [en] Computer programs have been used for a long time in the design of integrated circuits, specially for verification and simulation. In the 80s silicon compilers appeared, a newkind of tool used for circuit synthesis and layout generation. The system here presented permits the automatic generation of the layout of a datapath (a collection of registers and ALUs) from a specification containing the number of bits and functions desired. A gate matrix layout generator with facilities for placing terminals is also presented, as a tool for creating the necessary cells for the datapath library. The several problems involved on layout generation are discussed, as well as the solutions employed.

No description available.

The area of fault-handling in reconfigurable logic devices is one that continues to receive research attention in the field of engineering. Field Programmable Gate Arrays (FPGAs) are reconfigurable logic devices that have become an essential element in electronic hardware used for space applications, for instance deep space satellites. When electronic devices such as FPGAs are launched into space, they are relentlessly exposed to fault-inducing hazards such as high levels of radiation and extreme temperatures. The ability of the device to maintain and correct its functionality while experiencing these harsh conditions is vital to a successful mission by today's technological standards. Many techniques have been proposed for the purpose of detecting and repairing hardware faults that occur in reconfigurable logic devices. The implementation of a Genetic Algorithm (GA) as the means of repairing a faulty component has become a popular method among such techniques. A great deal of success has been demonstrated by the use of GAs in fault-repair, but there is room for improvement in the completeness of a given repair. This thesis addresses this issue by exploring the possible outcomes of implementing a voting system to work in parallel with a particular GA. Throughout the first two chapters, a general overview ofFPGAs and faulthandling techniques is provided. The advantages and disadvantages of each technique are mentioned to help re-emphasize the main purpose for the research being conducted. Once a solid background has been established regarding the main ideas behind this work, the thesis presents an in-depth description of the problem and the experimental approach that is taken. The work involves experiments which are run using a simulated FPGA that is coded in C++. A genetic algorithm is included in the program in order to simulate the repair process. By varying the parameters of the GA, as well as experimenting with the addition of a voting scheme to enhance the performance, meaningful results are discovered and presented. Fault-handling techniques proposed in the future will have a better idea of whether or not it would be beneficial to include a voting scheme to improve success.

The continuous evolution of digital technology we enjoy today is the result of ever shrinking, faster and cheaper transistors that make up the ubiquitous integrated circuits of our devices. Over the decades, the industry has gone from purely geometrical scaling to innovative solutions like high-k dielectrics combined with metal gates and FinFETs. A possible future is the use of high mobility materials such as Germanium for the active areas of a transistor instead of Silicon. As a step towards building devices on Ge, we characterize a gate last process with epitaxial deposition of Si0.75Ge0.25 source and drain areas on bulk Si wafers. Devices fabricated are proof-of-concept PMOSFETs and NMOSFETs with channel widths of 10 µm and 40 µm and channel lengths between 0.6 µm and 50 µm. The gate electrode of the fabricated devices is insitu doped polycrystalline Silicon. The devices are electrically characterized through I-V measurements and exhibit a yield of 95%. / Den konstanta utvecklingen av digital teknik som vi åtnjuter idag drivs av den ständiga utvecklingen av transistorer. Dessa blir mer kompakta, snabbare och kostar mindre för varje generation och bygger upp de integrerade kretsar som driver all vår vardagsteknik. Under ett tidsspann på flera decennier har krympningen gått från enbart geometrisk skalning till mer innovativa lösningar. Gate-oxiden har gått från rent kiseldioxid till material med lägre relativ permittivitet vilket möjliggjort en tunnare ekvivalent elektrisk tjocklek än vad som varit möjligt för kiseloxid. FinFet eller så kallade ’tri-gate’ transistorer har ersatt den plana varianten för att öka den ledande arean utan att enheterna sväller ut över substratet. En framtida möjlighet är även att använda material med högre mobilitet för elektroner och hål än kisel där en möjlig kandidat är Germanium. Som ett steg mot målet at bygga Germanium-transistorer tillverkar vi här gate last transistorer med source och drain i in-situ dopad kisel-germanium. Dessa konceptenheter används för att definiera och utveckla tillverkningsprocessen och tillverkas i flera omgångar. Varje skiva innehåller transistorer med en bredd på 40 µm och 10 µm. Kanallängden på transistorerna går mellan 0.6 µm och 50 µm för båda bredderna och av varje enhet finns 101 stycken per kiselskiva (100 mm diameter). Gate-elektroden består i samtliga fall av in-situ dopat poly-kristallint kisel. Enheterna karaktäriseras därefter genom elektriska mätningar och mätdata analyseras och sammanställs. Det visas genom dessa mätningar att ett utfall om över 95% fungerande enheter kan uppnås med processen.

The thesis Is concerned with the development of a separately excited DC machine In which gate turn-off thyristor devices with their associated firing and protective circuits are used to provide the static commutation of armature coil current. The developed machine has Its armature winding with 24 tapping points located on the stator and Interconnected In "Lop" configuration. The Initiation of the conduction periods of armature switching devices Is defined by a digital control logic circuit. In conjunction with an Incremental rotary encoder which provides the necessary feedback Information relating to shaft speed and shaft angular position. This Is arranged such that, under normal running conditions of the machine, the axis of the radial field of the armature winding maintains the normal space-quadrature relationship with that of the main field winding, giving the optimal torque angle of 000. Provision Is made, however, within the digital control circuit for controlled departure of the armature switch tapping points from the quadrature axis positions, and the effect of this, In Improving commutation Is Investigated. The effect of Interpoles Is also explored. On the basis of the analysis carried out, a proposal Is made for the future development of the machine employing a reduced number of armature switching devices without the need for Interpole windings. / Electricity Directorate, Ministry of Works, Power and Water, Manama, Bahrain.

There are many types of power sources that are used for many different applications. In this thesis, a programmable source is designed, built and tested. The programmable source is able to generate three-phase output signals from three different input voltage signals using the ADMC401 DSP board. The programmable source is unique in that it can reproduce any input signal and amplify the input signal. This is done by pulse-width modulation (PWM). The programmable source was designed with gate driver circuits, a motor controller, switches, filters, comparators and other electronic components. Thermal protection and applications for this programmable source are presented in this thesis. Also, test data taken when a squirrel cage induction motor was powered by the programmable source is presented.