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No description available.

No description available.

No description available.

No description available.

The Gate Turn-Off (GTO) Thyristor has the best voltage blocking and current conducting capabilities among all known high power semiconductor devices. To improve its dynamic performances to meet the increased demand in high-performance high-power applications, a special driving technique, namely unity gain turn-off, is studied. Several innovative approaches, which realize this driving requirement, are proposed, analyzed and experimentally demonstrated in this dissertation. The Emitter Turn-Off Thyristor (ETO) is a new family of high power semiconductor devices that is suitable for megawatt power electronics application. ETOs with voltage and current ratings of 4.0~6.0 kV and 1.0~4.0 kA, have been developed and demonstrated. These power levels are the highest in silicon power devices and are comparable to those of the GTO. Compared to the conventional GTO, the ETO has a much shorter storage time, voltage controlled turn-off capability, and a much larger reverse biased safe operation area (RBSOA). These combined advantages make the ETO based power system simpler in terms of dv/dt snubber, di/dt snubber and over current protection, resulting in significant savings at the system level. Experimental and numerical simulation results that demonstrate the advantages of the ETO are presented. A new family of snubberless turn-off GTO, the Resonant Gate Commutated Thyristor (RGCT) is proposed and investigated. By using a transient high commutation voltage, the RGCT can achieve unity turn-off gain and snubberless turn-off capability even with a relatively high gate loop stray inductance. Therefore conventional GTOs with flexible gate lead can be used to achieve the state-of-the-art performance similar to that of the Integrated Gate Commutated Turn-Off thyristor (IGCT). Detailed current commutation analysis and experimental results are presented. A novel equivalent circuit model for the GTO under the unity gain turn-off is proposed. This model is composed of a step current source, which represents the open-base PNP turn-off behavior, in series with a diode that represents the GTO's gate-cathode junction. This equivalent circuit can be used to analyze the turn-off transient behavior of a system employing this GTO. A new mechanism that dominates the failure of the GTO under the unity gain turn-off condition is identified and analyzed. Innovative hybrid GTO-based devices all have significant gate lead stray inductance. During the turn-off transition, this stray inductor will interact with the turn-off voltage source, the junction capacitance of the GTO's gate-cathode, causing effective current injection into the GTO's emitter junction when the voltage on the device is already high. Design guidelines and solutions for different types of GTO-based hybrid devices are provided. / Ph. D.

The proposed demodulator is an all-digital implementation of a FM demodulator. The proposed design intends to implement a FM demodulator for high-speed applications, which makes the requirements for analog components minimal. The proposed circuit is an all-digital quadrature demodulator, where the individual components have been implemented without using any multipliers. The topology uses a Pulse width modulation (PWM) block to avoid the need for a DAC. The Xilinx virtex-7 FPGA has been used as the reference device for the work. The circuit is validated through behavioral simulations and the results conclude the proposed circuit demodulates the targeted FM channel and provides the spectrum information for the targeted FM channel / Master of Science / With the rise in popularity of reconfigurable hardware, such as FPGAs, digital signal processing has become one of the most widespread usage of such devices. The major advantage of using FPGAs for implementing signal processing algorithms is that they provide very less time to market and can be re-modeled or modified in easily. Moreover, the netlists designed for FPGAs can be easily translated to ASICs. As wireless communication has become omnipresent, modulation and demodulation schemes have become an area of great interest. With the increase in data rates for the modern-day communication systems, the digital implementation of these algorithms is becoming more and more common. This is further aided by the advancements in high-speed ADCs and the Electronic Design Automation (EDA) tools, which have made the usage of FPGAs lot more feasible and a lot more efficient. This work discusses the demodulation scheme for one of the most widespread modulation algorithms, Frequency Modulation (FM). An all-digital FM demodulator design is proposed for highspeed implementation on FPGAs. The proposed design is an all-digital quadrature I-Q based demodulator.

Use of traditional gate level test generation techniques is prohibitively expensive and time consuming for VLSI chips. High level approaches to test generation have been proposed to improve the efficiency of test generation, e.g., the Behavioral Test Generator developed at Virginia Tech generates test vectors from high level Behavioral VHDL descriptions. To validate the utility of these test vectors, it needs to be established that they provide adequate coverage at the gate level. This thesis shows that test vectors obtained from the Behavioral Test Generator provide adequate coverage for the equivalent gate level circuit. A system that was developed to effectively evaluate the test vectors is presented. The implementation of Heuristic Test Generator to improve the coverage of the Behavioral Test Generator is explained. / Master of Science

With the use of the simplistic equivalent circuits, loss mechanism in conventional power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) gate drive circuits is analyzed. Resonant gate drive techniques are investigated and a new resonant gate drive circuit is presented. The presented circuit adds minor complexity to conventional gate drivers but reduces the MOSFET gate drive loss very effectively. To further expand its use in driving Half-Bridge MOSFETs, another circuit is proposed in this thesis. The later circuit simplifies the isolation circuitry for the top MOSFET and meanwhile consumes much lower power than conventional gate drivers. / Master of Science

This study examined framing in two Bulgarian television stations and their web sites. Framing within the web sites' news coverage of the United States was examined during the one-month period immediately following the 2008 United States presidential election. The news articles gathered from the two web sites were examined for amount of coverage, frame presence and valence, as well as hyperlinks, in order to offer insight into the fields of gatekeeping, framing, and corporate ownership bias. Suggestions of bias were found in terms of the overall tone of the articles but not in the amount of coverage. There was a significant difference between the two web sites in the tone of coverage concerning individuals and events. / Master of Arts