Thesis (PhD)--University of Stellenbosch, 2003. / ENGLISH ABSTRACT: The development of a tool kit for the design of superconducting programmable gate arrays (SPGAs) is discussed. A circuit optimizer using genetic algorithms is developed and evaluated. Techniques and a program are also developed for the generation of segmentized 3D models with which to calculate inductance in circuit structures through FastHenry. The ability to add random variations to the dimensions of the models is included. These tools are then used to design novel latching elements that allow the construction of reprogrammable Rapid Single Flux Quantum (RSFQ) circuits. A circular process is used, whereby layouts are converted back to circuit diagrams through element extraction, and reoptimized if necessary. Two programmable frequency dividers are then designed; one for testing the routing and switch structures and programming architecture of an SPGA, and another compact one for testing the latching elements and off-chip interface. The dissertation concludes with an overview of the circuits necessary for the implementation of a fully functional SPGA. / AFRIKAANSE OPSOMMING: Die ontwikkeling van ’n gereedskapstel vir die ontwerp van supergeleier FPGA’s (SPGA’s) word bespreek. Eerstens word ’n stroombaanoptimeerder, wat met genetiese algoritmes funksioneer, ontwikkel en geëvalueer. Daarna word tegnieke en ’n program ontwikkel om driedimensionele segmentmodelle te genereer waaruit FastHenry die induktansie van stroombaanstrukture kan bepaal. Die vermoë om toevalsveranderinge by die dimensies van die modelle te voeg, is ook ingesluit. Hierdie gereedskap word dan gebruik om nuwe grendelelemente te ontwerp waarmee herprogrammeerbare Rapid Single Flux Quantum (RSFQ) stroombane gebou kan word. ’n Sirkulêre proses word gevolg, waarvolgens uitlegte na stroombaandiagramme teruggeskakel kan word (deur elementonttrekkings) en, indien nodig, heroptimeer kan word. Twee programmeerbare frekwensiedelers word daarna ontwerp; een om die pulsvervoer- en skakelstrukture, asook programmeringsargitektuur van ’n SPGA te toets, en ’n ander, kompakter een om die grendelelemente en warmlogika koppelvlakke mee te toets. Die proefskrif sluit af met ’n oorsig oor die stroombane benodig vir die implementering van ’n volledig funksionele SPGA.

published_or_final_version / Industrial and Manufacturing Systems Engineering / Doctoral / Doctor of Philosophy

In recent years, both hafnia and zirconia have been looked at closely in the quest for a high permittivity gate dielectric to replace silicon dioxide in advanced metal oxide semiconductor field effect transistors (MOSFET). Hafnium dioxide or HfO2 is chosen for its high dielectric constant (five times that of SiO2) and compatibility with stringent requirements of the Si process. As deposited, thin hafnia films are typically amorphous but turn polycrystalline after a post-deposition anneal. To control the phase composition in hafnia films understanding of structural phase transitions is a first step. In this dissertation using first principles methods we consider three phase transitions of hafnia and zirconia: monoclinic to tetragonal, tetragonal to cubic and amorphous to crystalline. Because the high surface to volume ratio in hafnia films and powders plays an important role in phase transitions, we also study the surface properties of hafnia. We discuss the mechanisms of various phase transitions and theoretically estimate the transition temperatures. We find two types of amorphous hafnia and show that they have different structural and electronic properties. The small energy barrier between the amorphous and crystalline structures is found to cause the low crystallization temperature. Moreover, we calculate work functions and surface energies for hafnia surfaces and show the surface suppression of the phase transitions. / text

Hafnium and Zirconium based gate dielectrics are considered potential candidates to replace SiO2 or SiON as the gate dielectric in CMOS processing. Furthermore, the addition of nitrogen into this pseudo-binary alloy has been shown to improve their thermal stability, electrical properties, and reduce dopant penetration. Because CMOS processing requires high temperature anneals (up to 1050 °C), it is important to understand the diffusion properties of any metal associated with the gate dielectric in silicon at these temperatures. In addition, dopant penetration from the doped polysilicon gate into the Si channel at these temperatures must also be studied. Impurity outdiffusion (Hf, Zr) from the dielectric, or dopant (B, As, P) penetration through the dielectric into the channel region would likely result in deleterious effects upon the carrier mobility. In this dissertation extensive thermal stability studies of alternate gate dielectric candidates ZrSixOy and HfSixOy are presented. Dopant penetration studies from doped-polysilicon through HfSixOy and HfSixOyNz are also presented. Rutherford backscattering spectroscopy (RBS), heavy ion RBS (HI-RBS), x-ray photoelectron spectroscopy (XPS), high resolution transmission electron microscopy (HR-TEM), and time of flight and dynamic secondary ion mass spectroscopy (ToF-SIMS, D-SIMS) methods were used to characterize these materials. The dopant diffusivity is calculated by modeling of the dopant profiles in the Si substrate. In this disseration is reported that Hf silicate films are more stable than Zr silicate films, from the metal interdiffusion point of view. On the other hand, dopant (B, As, and P) penetration is observed for HfSixOy films. However, the addition of nitrogen to the Hf - Si - O systems improves the dopant penetration properties of the resulting HfSixOyNz films.

This thesis presents thermal and power loss models of a three phase IGBT voltage source inverter used in the design of the 625KW fuel cell and reformer demonstration which is a top priority for the Office of Naval Research. The ability to generate thermal simulations of systems and to accurately predict a system's response becomes essential in order to reduce the cost of design and production, increase reliability, quantify the accuracy of the estimated thermal impedance of an IGBT module, predict the maximum switching frequency without violating thermal limits, predict the time to shutdown on a loss of coolant casualty, and quantify the characteristics of the heat-sink needed to dissipate the heat under worst case conditions. In order to accomplish this, power loss and thermal models were created and simulated to represent a three phase IGBT voltage source inverter in the lab. The simulated power loss and thermal model data were compared against the experimental data of a three phase voltage source inverter set up in the Naval Postgraduate School power systems laboratory.

The purpose of this thesis is to investigate factors which influences product launch strategies.

Submitted by Caroline Xavier (caroline.xavier@pucrs.br) on 2017-06-30T17:45:25Z No. of bitstreams: 1 DIS_CAROLINE_MACHADO_DARTORA_COMPLETO.pdf: 2382956 bytes, checksum: 7909b8673eceb86e85c844ad70245e3b (MD5) / Made available in DSpace on 2017-06-30T17:45:25Z (GMT). No. of bitstreams: 1 DIS_CAROLINE_MACHADO_DARTORA_COMPLETO.pdf: 2382956 bytes, checksum: 7909b8673eceb86e85c844ad70245e3b (MD5) Previous issue date: 2017-03-29 / The statistical nature of the physical process involved in Nuclear Medicine exams makes the use of Monte Carlo methods an useful tool for deposited energy and absorbed dose calculations on organs, mainly for risk-benefits assessment. Pregnant are important target for risk-benefit assessment, due the fetus exposure to radiation. Nuclear Medicine exams may generate fetus dose, either by irradiation due to maternal organs, or by activity that crosses the placenta and accumulates in fetus. Usually, both internal dosimetry estimation software and virtual anthropomorphic simulators are proprietary. The aim of this research is to investigate the use of GATE (Geant4 Application for Emission Tomography) application of Monte Carlo method on internal dosimetry calculation in simulated Nuclear Medicine image exams in pregnant woman. First, an evaluation of the use of GATE was performed to build dose maps with simple geometries. An evaluation of the radiation interaction behavior with respect to available GATE source types of configuration of single photon (99mTc) and positrons (18F) emitters was also performed. Dose estimation on a fetus was performed by simulation of a [18F] FDG distribution in a virtual 24-week pregnant woman simulator, Katja, with data based on literature. It was evaluated the impact on fetal dose of the mother bladder uptake of , placenta uptake, maternal organs irradiation and dose generated due to the uptake only in the fetus. The total estimated dose for a fetus on 24 weeks was 0.0122 mGy/MBq, in agreement with published data. Several individual dose contributions in the fetus that are not commonly found in the literature, such as the contribution due to the bladder (13%) and placenta (0.53%) were obtained. The contribution in total fetal dose of the activity only in the organs of the fetus was analyzed, resulting in 3.8%, where 56% is due only to positron emitted by the source. In conclusion, GATE generates dose maps that can be used as a method of dose estimation in pregnant women in MN scans, giving detailed information about the individual contributions of maternal organs uptake. / A natureza estat?stica dos processos f?sicos nos exames de Medicina Nuclear faz com que o uso de m?todos de Monte Carlo seja ?til para c?lculos da energia depositada e da dose absorvida nos ?rg?os, principalmente para avalia??o de risco-benef?cio. Gr?vidas s?o um alvo importante para avalia??o risco-benef?cio devido ? exposi??o do feto ? radia??o. Exames de Medicina Nuclear podem gerar dose no feto, tanto pela irradia??o devido ? atividade nos ?rg?os maternos, como pela atividade que atravessa a placenta e se acumula no feto. Usualmente, os softwares de estimativa de dosimetria interna e os simuladores antropom?rficos virtuais s?o propriet?rios. O objetivo desta pesquisa ? investigar o uso do aplicativo gratuito de simula??o de Monte Carlo denominado GATE (Geant4 Application for Emission Tomography), no c?lculo da dosimetria interna em exames simulados de Medicina Nuclear em mulheres gr?vidas. Inicialmente, foi realizada uma avalia??o do uso do GATE na constru??o de mapas de dose com geometrias simples e o comportamento para diferentes configura??es dos tipos de fontes no aplicativo para emissores de f?ton ?nico (99mTc) e p?sitrons (18F). A estimativa de dose no feto foi realizada atrav?s da simula??o de uma distribui??o de [18F]FDG em um simulador virtual gratuito de mulher gr?vida de 24 semanas, denominada Katja, com distribui??o de atividade baseada na literatura. Foi investigado o impacto, na dose fetal total, da capta??o e esvaziamento da bexiga da m?e, da placenta, da irradia??o do feto pelos ?rg?os maternos e dose gerada devido ? atividade captada somente pelo feto. A dose estimada total para um feto de 24 semanas foi de 0,0122 mGy/MBq, estando de acordo com a m?dia dos trabalhos publicados. Obtiveram-se contribui??es individuais ? dose no feto que n?o s?o comumente encontradas na literatura, tais como a dose devido ? bexiga (13%) e ? placenta (0,53%). Foi analisada a contribui??o da atividade captada somente nos ?rg?os do feto na dose total no feto, que resultou em 3,8%, sendo que 56% correspondem ? dose devido aos p?sitrons emitidos pela fonte. Conclui-se que o aplicativo GATE gera mapas de dose que podem ser utilizados como um m?todo de estimativa de dose de mulheres gr?vidas em imagens de Medicina Nuclear, fornecendo informa??es detalhadas das contribui??es individuais da capta??o nos ?rg?os da m?e ? dose.

As the sizes of modern circuit designs become bigger and bigger, implementing those large circuits into FPGA become arduous. The state-of-the-art academic FPGA place-and-route tool, VPR, has good quality but needs around a whole day to complete a placement when the input circuit netlist contains millions of lookup tables, excluding the runtime needed for routing. / To speed up the placement process, we propose a routability-driven placement algorithm for FPGAs, which adopts techniques used in ASIC global placer. Our placer follows the lower-bound-and-upper-bound iterative optimization process in ASIC placers like Ripple. The total half perimeter wirelength (HPWL) of the circuit is used as the objective cost function and it modeled using the Bound2Bound net model. In lower bound computation, a placement solution with the minimum HPWL is determined by the conjugate gradient method. In upper bound computation, an almost-legalized result is produced by spreading cells linearly in the whole placement area. Those positions are then served as fixed-point anchors and fed into the next lower bound computation. Furthermore, global routing will be performed in the upper bound computation to estimate the routing segments usage, as a mean to consider congestion in the placement. The two bounds computations are computed alternatively until their results converge. / We tested our approach using 20 MCNC benchmarks and 16 large benchmarks for performance and scalability. Experimental results show that based on the island-style architecture which VPR is most optimized, our approach can obtain a placement result 8× faster than VPR with 2% more in channel width, or 3× faster with 1% more in channel width when considering congestion either. Our approach is even 20× faster in placing large benchmarks having over 50,000 lookup tables, however, with 10% more in channel width. Based on the Xilinx Virtex-5 architecture from a recent related work, we can out-perform VPR by reducing the channel width by 3% with almost 3× speedup in runtime. / 現今的電路設計得愈來愈大，要把這些巨大的電路實現在現場可程式邏輯門陣列(FPGA)上變得愈來愈困難，由其在布局及布線程序上變得十分耗時。儘管在一般的情況下，現時在學術領域中，最先進的用在FPGA上的布局及布線工具能夠提供高質素的布局結果，但當所需要布局的電路所包含的邏輯元件數達到數百萬個以上時，該工具也要耗費一整天的時間才能完成整個布局程序，其中並未計算之後布線程序所額外需要的時間。 / 有見及此，我們參考了一些應用在特殊應用積體電路(ASIC)設計軟體上的布局方法，並提出了一個專為FPGA而設的偏向優化Routability的布局算法來縮短布局程序所需要的時間。我們的算法以Bound2Bound模型來模擬電路內邏輯元件間的接線，並估算其Half-Perimeter線長(HPWL)來作為我們的目標函數進行優化。我們採用了一些ASIC布局軟體，如Ripple內的上限及下限交互計算的迭代優化程序。在下限的運算過程中，我們在無視節點重疊的情況下，使用了共軛梯度法來找出HPWL的最少值。在上限的運算過程中，我們把在下限計算找到的結果平均散佈在整個可布局的區域內，從而減少節點重疊的情況來得出一接近有效的布局結果。接著，這些節點的位置會被用作定點錨，附加在下一次的下限計算中，並引導它得出一節點重疊相對較少的布局結果。此外，我們可以選擇在上限的運算過程中加入Global Routing程序來估計該布局結果所需的線段數，從而在布局過程中考慮布線過份擁塞的情況。上限及下限的計算會不斷交互進行，直至雙方所得的結果聚合為止。 / 我們使用了20個MCNC基準電路及16個大型基準電路，來測試我們的布局算法的性能和可擴展性。實驗結果指出，針對島狀結構的FPGA，我們的算法能夠比VPR快8倍得出布局結果，但其通道寬度(Channel Width)卻增加了2%。如果在考慮布線擁塞度的情況下，我們的算法能夠比VPR快3倍，但其通道寬度卻增加了1%。再者，對於一些擁有超過50000個邏輯元件的大型基準電路，相比於VPR，雖然我們的算法能夠提供20倍的速度增長，但其布局結果的通道寬度卻增加了10%。如果我們使用在最近的相關研究中使用的Xilinx Virtex-5結構的話，我們的算法能夠比VPR快接近3倍得出布局結果，並且減少約3%的通道寬度。 / Lam, Ka Chun. / Thesis M.Phil. Chinese University of Hong Kong 2014. / Includes bibliographical references (leaves 64-70). / Abstracts also in Chinese. / Title from PDF title page (viewed on 12, October, 2016). / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only.

by C.H. Fung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1989. / Bibliography: leaves [81-82]

Chu-Keung Chung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1999. / Includes bibliographical references (leaves 88-92). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgments --- p.iii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation and Aims --- p.1 / Chapter 1.2 --- Contributions --- p.3 / Chapter 1.3 --- Structure of the Thesis --- p.4 / Chapter 2 --- Literature Review --- p.6 / Chapter 2.1 --- Introduction --- p.6 / Chapter 2.2 --- Complete Algorithms --- p.7 / Chapter 2.2.1 --- Parallel Checking --- p.7 / Chapter 2.2.2 --- Mom's --- p.8 / Chapter 2.2.3 --- Davis-Putnam --- p.9 / Chapter 2.2.4 --- Nonchronological Backtracking --- p.9 / Chapter 2.2.5 --- Iterative Logic Array (ILA) --- p.10 / Chapter 2.3 --- Incomplete Algorithms --- p.11 / Chapter 2.3.1 --- GENET --- p.11 / Chapter 2.3.2 --- GSAT --- p.12 / Chapter 2.4 --- Summary --- p.13 / Chapter 3 --- Algorithms --- p.14 / Chapter 3.1 --- Introduction --- p.14 / Chapter 3.2 --- Tree Search Techniques --- p.14 / Chapter 3.2.1 --- Depth First Search --- p.15 / Chapter 3.2.2 --- Forward Checking --- p.16 / Chapter 3.2.3 --- Davis-Putnam --- p.17 / Chapter 3.2.4 --- GRASP --- p.19 / Chapter 3.3 --- Incomplete Algorithms --- p.20 / Chapter 3.3.1 --- GENET --- p.20 / Chapter 3.3.2 --- GSAT Algorithm --- p.22 / Chapter 3.4 --- Summary --- p.23 / Chapter 4 --- Field Programmable Gate Arrays --- p.24 / Chapter 4.1 --- Introduction --- p.24 / Chapter 4.2 --- FPGA --- p.24 / Chapter 4.2.1 --- Xilinx 4000 series FPGAs --- p.26 / Chapter 4.2.2 --- Bitstream --- p.31 / Chapter 4.3 --- Giga Operations Reconfigurable Computing Platform --- p.32 / Chapter 4.4 --- Annapolis Wildforce PCI board --- p.33 / Chapter 4.5 --- Summary --- p.35 / Chapter 5 --- Implementation --- p.36 / Chapter 5.1 --- Parallel Graph Coloring Machine --- p.36 / Chapter 5.1.1 --- System Architecture --- p.38 / Chapter 5.1.2 --- Evaluator --- p.39 / Chapter 5.1.3 --- Finite State Machine (FSM) --- p.42 / Chapter 5.1.4 --- Memory --- p.43 / Chapter 5.1.5 --- Hardware Resources --- p.43 / Chapter 5.2 --- Serial Graph Coloring Machine --- p.44 / Chapter 5.2.1 --- System Architecture --- p.44 / Chapter 5.2.2 --- Input Memory --- p.46 / Chapter 5.2.3 --- Solution Store --- p.46 / Chapter 5.2.4 --- Constraint Memory --- p.47 / Chapter 5.2.5 --- Evaluator --- p.48 / Chapter 5.2.6 --- Input Mapper --- p.49 / Chapter 5.2.7 --- Output Memory --- p.49 / Chapter 5.2.8 --- Backtrack Checker --- p.50 / Chapter 5.2.9 --- Word Generator --- p.51 / Chapter 5.2.10 --- State Machine --- p.51 / Chapter 5.2.11 --- Hardware Resources --- p.54 / Chapter 5.3 --- Serial Boolean Satisfiability Solver --- p.56 / Chapter 5.3.1 --- System Architecture --- p.58 / Chapter 5.3.2 --- Solutions --- p.59 / Chapter 5.3.3 --- Solution Generator --- p.59 / Chapter 5.3.4 --- Evaluator --- p.60 / Chapter 5.3.5 --- AND/OR --- p.62 / Chapter 5.3.6 --- State Machine --- p.62 / Chapter 5.3.7 --- Hardware Resources --- p.64 / Chapter 5.4 --- GSAT Solver --- p.65 / Chapter 5.4.1 --- System Architecture --- p.65 / Chapter 5.4.2 --- Variable Memory --- p.65 / Chapter 5.4.3 --- Flip-Bit Vector --- p.66 / Chapter 5.4.4 --- Clause Evaluator --- p.67 / Chapter 5.4.5 --- Adder --- p.70 / Chapter 5.4.6 --- Random Bit Generator --- p.71 / Chapter 5.4.7 --- Comparator --- p.71 / Chapter 5.4.8 --- Sum Register --- p.71 / Chapter 5.5 --- Summary --- p.71 / Chapter 6 --- Results --- p.73 / Chapter 6.1 --- Introduction --- p.73 / Chapter 6.2 --- Parallel Graph Coloring Machine --- p.73 / Chapter 6.3 --- Serial Graph Coloring Machine --- p.74 / Chapter 6.4 --- Serial SAT Solver --- p.74 / Chapter 6.5 --- GSAT Solver --- p.75 / Chapter 6.6 --- Summary --- p.76 / Chapter 7 --- Conclusion --- p.77 / Chapter 7.1 --- Future Work --- p.78 / Chapter A --- Software Implementation of Graph Coloring in CHIP --- p.79 / Chapter B --- Density Improvements Using Xilinx RAM --- p.81 / Chapter C --- Bit stream Configuration --- p.83 / Bibliography --- p.88 / Publications --- p.93