Tsoi Kuen Hung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2002. / Includes bibliographical references (leaves 84-92). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Objectives --- p.3 / Chapter 1.3 --- Contributions --- p.3 / Chapter 1.4 --- Thesis Organization --- p.4 / Chapter 2 --- Background and Review --- p.6 / Chapter 2.1 --- Introduction --- p.6 / Chapter 2.2 --- Cryptographic Algorithms --- p.6 / Chapter 2.3 --- Cryptographic Applications --- p.10 / Chapter 2.4 --- Modern Reconfigurable Platforms --- p.11 / Chapter 2.5 --- Review of Related Work --- p.14 / Chapter 2.5.1 --- Montgomery Multiplier --- p.14 / Chapter 2.5.2 --- IDEA Cipher --- p.16 / Chapter 2.5.3 --- RC4 Key Search --- p.17 / Chapter 2.5.4 --- Secure Random Number Generator --- p.18 / Chapter 2.6 --- Summary --- p.19 / Chapter 3 --- The IDEA Cipher --- p.20 / Chapter 3.1 --- Introduction --- p.20 / Chapter 3.2 --- The IDEA Algorithm --- p.21 / Chapter 3.2.1 --- Cipher Data Path --- p.21 / Chapter 3.2.2 --- S-Box: Multiplication Modulo 216 + 1 --- p.23 / Chapter 3.2.3 --- Key Schedule --- p.24 / Chapter 3.3 --- FPGA-based IDEA Implementation --- p.24 / Chapter 3.3.1 --- Multiplication Modulo 216 + 1 --- p.24 / Chapter 3.3.2 --- Deeply Pipelined IDEA Core --- p.26 / Chapter 3.3.3 --- Area Saving Modification --- p.28 / Chapter 3.3.4 --- Key Block in Memory --- p.28 / Chapter 3.3.5 --- Pipelined Key Block --- p.30 / Chapter 3.3.6 --- Interface --- p.31 / Chapter 3.3.7 --- Pipelined Design in CBC Mode --- p.31 / Chapter 3.4 --- Summary --- p.32 / Chapter 4 --- Variable Radix Montgomery Multiplier --- p.33 / Chapter 4.1 --- Introduction --- p.33 / Chapter 4.2 --- RSA Algorithm --- p.34 / Chapter 4.3 --- Montgomery Algorithm - Ax B mod N --- p.35 / Chapter 4.4 --- Systolic Array Structure --- p.36 / Chapter 4.5 --- Radix-2k Core --- p.37 / Chapter 4.5.1 --- The Original Kornerup Method (Bit-Serial) --- p.37 / Chapter 4.5.2 --- The Radix-2k Method --- p.38 / Chapter 4.5.3 --- Time-Space Relationship of Systolic Cells --- p.38 / Chapter 4.5.4 --- Design Correctness --- p.40 / Chapter 4.6 --- Implementation Details --- p.40 / Chapter 4.7 --- Summary --- p.41 / Chapter 5 --- Parallel RC4 Engine --- p.42 / Chapter 5.1 --- Introduction --- p.42 / Chapter 5.2 --- Algorithms --- p.44 / Chapter 5.2.1 --- RC4 --- p.44 / Chapter 5.2.2 --- Key Search --- p.46 / Chapter 5.3 --- System Architecture --- p.47 / Chapter 5.3.1 --- RC4 Cell Design --- p.47 / Chapter 5.3.2 --- Key Search --- p.49 / Chapter 5.3.3 --- Interface --- p.50 / Chapter 5.4 --- Implementation --- p.50 / Chapter 5.4.1 --- RC4 cell --- p.51 / Chapter 5.4.2 --- Floorplan --- p.53 / Chapter 5.5 --- Summary --- p.53 / Chapter 6 --- Blum Blum Shub Random Number Generator --- p.55 / Chapter 6.1 --- Introduction --- p.55 / Chapter 6.2 --- RRNG Algorithm . . --- p.56 / Chapter 6.3 --- PRNG Algorithm --- p.58 / Chapter 6.4 --- Architectural Overview --- p.59 / Chapter 6.5 --- Implementation --- p.59 / Chapter 6.5.1 --- Hardware RRNG --- p.60 / Chapter 6.5.2 --- BBS PRNG --- p.61 / Chapter 6.5.3 --- Interface --- p.66 / Chapter 6.6 --- Summary --- p.66 / Chapter 7 --- Experimental Results --- p.68 / Chapter 7.1 --- Design Platform --- p.68 / Chapter 7.2 --- IDEA Cipher --- p.69 / Chapter 7.2.1 --- Size of IDEA Cipher --- p.70 / Chapter 7.2.2 --- Performance of IDEA Cipher --- p.70 / Chapter 7.3 --- Variable Radix Systolic Array --- p.71 / Chapter 7.4 --- Parallel RC4 Engine --- p.75 / Chapter 7.5 --- BBS Random Number Generator --- p.76 / Chapter 7.5.1 --- Size --- p.76 / Chapter 7.5.2 --- Speed --- p.76 / Chapter 7.5.3 --- External Clock --- p.77 / Chapter 7.5.4 --- Random Performance --- p.78 / Chapter 7.6 --- Summary --- p.78 / Chapter 8 --- Conclusion --- p.81 / Chapter 8.1 --- Future Development --- p.83 / Bibliography --- p.84

Zhou Lin. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2004. / Includes bibliographical references (leaves 50-53). / Abstracts in English and Chinese. / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Aims and Contribution --- p.3 / Chapter 1.3 --- Thesis Overview --- p.4 / Chapter 2 --- Field-Programmable Gate Array and Routing Algorithm in VPR --- p.6 / Chapter 2.1 --- Commercially Available FPGAs --- p.6 / Chapter 2.2 --- FPGA Logic Block Architecture --- p.7 / Chapter 2.2.1 --- Logic Block Functionality vs. FPGA Area-Efficiency --- p.7 / Chapter 2.2.2 --- Logic Block Functionality vs. FPGA Delay-Performance --- p.7 / Chapter 2.2.3 --- Lookup Table-Based FPGAs --- p.8 / Chapter 2.3 --- FPGA Routing Architecture --- p.8 / Chapter 2.4 --- Design Parameters of FPGA Routing Architecture --- p.10 / Chapter 2.5 --- CAD for FPGAs --- p.10 / Chapter 2.5.1 --- Synthesis and Logic Block Packing --- p.11 / Chapter 2.5.2 --- Placement --- p.11 / Chapter 2.5.3 --- Routing --- p.12 / Chapter 2.5.4 --- Delay Modelling --- p.13 / Chapter 2.5.5 --- Timing Analysis --- p.13 / Chapter 2.6 --- FPGA Programming Technologies --- p.13 / Chapter 2.7 --- Routing Algorithm in VPR --- p.14 / Chapter 2.7.1 --- Pathfinder Negotiated Congestion Algorithm --- p.14 / Chapter 2.7.2 --- Routing Algorithm Used by VPR --- p.16 / Chapter 3 --- Connection-Switch Box Design --- p.17 / Chapter 3.1 --- Introduction --- p.17 / Chapter 3.2 --- Connection-Switch Box Design Algorithm --- p.19 / Chapter 3.2.1 --- Connection between Logic Pins and Tracks --- p.20 / Chapter 3.2.2 --- Connection between Pad Pins and Tracks --- p.25 / Chapter 3.3 --- Switch Number Comparisons --- p.26 / Chapter 3.4 --- Experimental Results --- p.29 / Chapter 3.5 --- Summary --- p.32 / Chapter 4 --- Optimal MST-Based Graph Algorithm on FPGA Segmenta- tion Design --- p.37 / Chapter 4.1 --- Introduction --- p.37 / Chapter 4.2 --- MST-Based Graph Algorithm on FPGA Channel Segmentation Design --- p.39 / Chapter 4.2.1 --- Net Merging Problem of Row-Based FPGAs --- p.41 / Chapter 4.2.2 --- Extended Net Merging Problem of Symmetrical Array FPGAs --- p.44 / Chapter 4.3 --- Experimental Results --- p.46 / Chapter 4.4 --- Summary --- p.46 / Chapter 5 --- Conclusions --- p.48 / Bibliography --- p.50

投影機相機(projector camera)系統近年相當流行，主要原因是它能夠靈活地展示影像，使用戶有更大的自由度作出操作。手提式投影機的技術在過往幾年急速發展、漸見成熟，知名的家用電子産品生産廠閱始推出内置迷你投影機的手機和攝影機。另一方面手機的運算能力正急劇地提升，它們多都配置不同種類且功能强大的周邊設備。 / 本論文提出並討論一種基於現場可编程邏輯閘陣列(Field Programmable Gate Array, FPGA),並適用於嵌入式系统的特殊處理器。該特殊處理器專門處理來自相機的資料串流，透過一系列的象素圖像處理運算如圖像梯度和高斯模糊，去找出相中物件的邊緣，藉此分擔微處器在運算上的負擔。實驗結果明這特殊處理器可實現於低端的FPGA上並和普遍的微處器一起運作。 / 本論文第二個探討的主題是一個利用多模卡爾曼濾波器(Multiple Model Kalman Filter)的直線追踪器，並利用多個直線追踪器去作投影面板的追踪。利用卡爾曼濾波器只需要很低的運算能力的優點,我們的直線追踪器在嵌入式系统實測時能達到每秒200幀的速度。多模卡爾曼濾波器在實驗中有滿意的成績並較單卡爾曼濾波器和擴展卡爾曼濾波器優異。 / Projector-camera (ProCam in short) systems are getting very popular since the user can change the display area dynamically and enjoy more freedom in handling the device. In recent years, the mobile projector technology is becoming mature and manufacturers are shipping mobile phones and digital cameras with projectors. On the other hand, the computation power of a cell phone had dramatically increased and the cell phones are accompanied with large number of powerful peripherals. / In this thesis, the possibility of making an embedded Projector-camera (ProCam) system is investigated. A ProCam system is developed by our research group previously and designed for desktop Personal Computers(PCs). The system uses computer vision techniques to detect a white cardboard as the projection screen and uses particle filter to trace the screen in subsequent frames. The system demands a large computation power, unfortunately the power of low cost embedded system is still not powerful enough to implement the ProCam system.Therefore, specially designed hardware and computationally efficient algorithm are required in order to implement the ProCam system on an embedded system. / An FPGA based special processor to share the workload of the microcontroller in the embedded system is proposed and tested. This special processor will take the data stream of the camera as the inputs and apply pixel-wise image operators such as image gradient and Gaussian blur in order to extract the edge pixels. As a result, the workload of the microcontroller in the embedded system is reduced. The experiments show that the design can be implement on a low-end FPGA with a simple microcontroller. / A line tracker using Multiple Model Kalman lter is also proposed in this thesis. The aim of this tracker is to reduce the time on tracking the board. Benet from the low computation requirement of Kalman filter, the proposed line tracker can run in 200 fps on our testing embedded system. The experiments also show that the robustness of the Multiple Model Kalman filter is satisfactory and it outperforms the line trackers using single Kalman filter or extended Kalman filter alone. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Detailed summary in vernacular field only. / Fung, Hung Kwan. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2012. / Includes bibliographical references (leaves 115-124). / Abstracts also in Chinese. / Abstract --- p.ii / Acknowledgement --- p.v / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation and Objective --- p.1 / Chapter 1.2 --- Contributions --- p.3 / Chapter 1.3 --- Thesis Organization --- p.5 / Chapter 2 --- Background --- p.7 / Chapter 2.1 --- Introduction --- p.7 / Chapter 2.2 --- Projector-Camera System --- p.8 / Chapter 2.2.1 --- Static Projector-Screen --- p.9 / Chapter 2.2.2 --- Dynamic Projector-Screen --- p.13 / Chapter 2.3 --- Embedded Vision --- p.15 / Chapter 2.4 --- Summary --- p.25 / Chapter 3 --- System Overview --- p.26 / Chapter 3.1 --- System Design --- p.26 / Chapter 3.2 --- Our Approach --- p.28 / Chapter 3.2.1 --- Projector-camera system --- p.28 / Chapter 3.2.2 --- Smart Camera --- p.31 / Chapter 3.2.3 --- Quadrangle Detection and Tracking Module --- p.32 / Chapter 3.2.4 --- Projection Module --- p.32 / Chapter 3.3 --- Extension --- p.33 / Chapter 4 --- Smart Camera --- p.34 / Chapter 4.1 --- Introduction --- p.34 / Chapter 4.2 --- Hardware Overview --- p.35 / Chapter 4.3 --- Image Acquisition --- p.40 / Chapter 4.4 --- Image Processing --- p.42 / Chapter 4.4.1 --- RGB-to-Gray Conversion Module . --- p.44 / Chapter 4.4.2 --- Image Smoothing Module --- p.45 / Chapter 4.4.3 --- Image Gradient Module --- p.49 / Chapter 4.4.4 --- Non-maximum Suppression and Hysteresis Thresholding --- p.53 / Chapter 4.5 --- Summary --- p.55 / Chapter 5 --- Quadrangle Detection and Tracking --- p.57 / Chapter 5.1 --- Introduction --- p.57 / Chapter 5.2 --- Line Feature Extraction --- p.61 / Chapter 5.3 --- Automatic Quadrangle Detection --- p.62 / Chapter 5.4 --- Real-time Quadrangle Tracking --- p.68 / Chapter 5.4.1 --- Line Tracker --- p.69 / Chapter 5.5 --- Tracking Lose Strategy --- p.76 / Chapter 5.6 --- Recover from Tracking Failure --- p.77 / Chapter 5.7 --- Summary --- p.77 / Chapter 6 --- Implementation and Experiment Result --- p.79 / Chapter 6.1 --- Introduction --- p.79 / Chapter 6.2 --- Smart Camera --- p.79 / Chapter 6.3 --- Line Tracking --- p.87 / Chapter 7 --- Limitation and Discussion --- p.101 / Chapter 7.1 --- Introduction --- p.101 / Chapter 7.2 --- Limitation --- p.101 / Chapter 7.3 --- Summary --- p.105 / Chapter 8 --- Application --- p.107 / Chapter 8.1 --- Introduction --- p.107 / Chapter 8.2 --- Portable Projector-Camera System --- p.107 / Chapter 8.3 --- Summary --- p.110 / Chapter 9 --- Conclusion --- p.112 / Bibliography --- p.115

Cheung Chak Chung. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 101-114). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgments --- p.iii / Vita --- p.v / Table of Contents --- p.vi / List of Figures --- p.x / List of Tables --- p.xiv / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation --- p.1 / Chapter 1.2 --- Aims and Contribution --- p.4 / Chapter 1.3 --- Thesis Overview --- p.5 / Chapter 2 --- VLSI Design Cycle --- p.6 / Chapter 2.1 --- Logic Synthesis --- p.7 / Chapter 2.1.1 --- Logic Minimization --- p.8 / Chapter 2.1.2 --- Technology Mapping --- p.8 / Chapter 2.1.3 --- Testability --- p.8 / Chapter 2.2 --- Physical Design Synthesis --- p.8 / Chapter 2.2.1 --- Partitioning --- p.9 / Chapter 2.2.2 --- Floorplanning & Placement --- p.10 / Chapter 2.2.3 --- Routing --- p.11 / Chapter 2.2.4 --- "Compaction, Extraction & Verification" --- p.12 / Chapter 2.2.5 --- Physical Design of FPGAs --- p.12 / Chapter 3 --- Alternative Wiring --- p.13 / Chapter 3.1 --- Introduction --- p.13 / Chapter 3.2 --- Notation and Definitions --- p.15 / Chapter 3.3 --- Application of Rewiring --- p.17 / Chapter 3.3.1 --- Logic Optimization --- p.17 / Chapter 3.3.2 --- Timing Optimization --- p.17 / Chapter 3.3.3 --- Circuit Partitioning and Routing --- p.18 / Chapter 3.4 --- Logic Optimization Analysis --- p.19 / Chapter 3.4.1 --- Global Flow Optimization --- p.19 / Chapter 3.4.2 --- OBDD Representation --- p.20 / Chapter 3.4.3 --- Automatic Test Pattern Generation (ATPG) --- p.22 / Chapter 3.4.4 --- Graph Based Alternative Wiring (GBAW) --- p.23 / Chapter 3.5 --- Augmented GBAW --- p.26 / Chapter 3.6 --- Logic Optimization by using GBAW --- p.28 / Chapter 3.7 --- Conclusions --- p.31 / Chapter 4 --- Multi-way Partitioning using Rewiring Techniques --- p.33 / Chapter 4.1 --- Introduction --- p.33 / Chapter 4.2 --- Circuit Partitioning Algorithm Analysis --- p.38 / Chapter 4.2.1 --- The Kernighan-Lin (KL) Algorithm --- p.39 / Chapter 4.2.2 --- The Fiduccia-Mattheyses (FM) Algorithm --- p.42 / Chapter 4.2.3 --- Geometric Representation Algorithm --- p.46 / Chapter 4.2.4 --- The Multi-level Partitioning Algorithm --- p.49 / Chapter 4.2.5 --- Hypergraph METIS - hMETIS --- p.51 / Chapter 4.3 --- The GBAW Partitioning Algorithm --- p.53 / Chapter 4.4 --- Experimental Results --- p.56 / Chapter 4.5 --- Conclusions --- p.58 / Chapter 5 --- Optimum FPGA Switch-Box Designs - HUSB --- p.62 / Chapter 5.1 --- Introduction --- p.62 / Chapter 5.2 --- Background and Definitions --- p.65 / Chapter 5.2.1 --- Routing Architectures --- p.65 / Chapter 5.2.2 --- Global Routing --- p.67 / Chapter 5.2.3 --- Detailed Routing --- p.67 / Chapter 5.3 --- FPGA Router Comparison --- p.69 / Chapter 5.3.1 --- CGE --- p.69 / Chapter 5.3.2 --- SEGA --- p.70 / Chapter 5.3.3 --- TRACER --- p.71 / Chapter 5.3.4 --- VPR --- p.72 / Chapter 5.4 --- Switch Box Design --- p.73 / Chapter 5.4.1 --- Disjoint type switch box (XC4000-type) --- p.73 / Chapter 5.4.2 --- Anti-symmetric switch box --- p.74 / Chapter 5.4.3 --- Universal Switch box --- p.74 / Chapter 5.4.4 --- Switch box Analysis --- p.75 / Chapter 5.5 --- Terminology --- p.77 / Chapter 5.6 --- "Hyper-universal (4, W)-design analysis" --- p.82 / Chapter 5.6.1 --- "H3 is an optimum (4, 3)-design" --- p.84 / Chapter 5.6.2 --- "H4 is an optimum (4,4)-design" --- p.88 / Chapter 5.6.3 --- "Hi is a hyper-universal (4, i)-design for i = 5,6,7" --- p.90 / Chapter 5.7 --- Experimental Results --- p.92 / Chapter 5.8 --- Conclusions --- p.95 / Chapter 6 --- Conclusions --- p.99 / Chapter 6.1 --- Thesis Summary --- p.99 / Chapter 6.2 --- Future work --- p.100 / Chapter 6.2.1 --- Alternative Wiring --- p.100 / Chapter 6.2.2 --- Partitioning Quality --- p.100 / Chapter 6.2.3 --- Routing Devices Studies --- p.100 / Bibliography --- p.101 / Chapter A --- 5xpl - Berkeley Logic Interchange Format (BLIF) --- p.115 / Chapter B --- Proof of some 2-local patterns --- p.122 / Chapter C --- Illustrations of FM algorithm --- p.124 / Chapter D --- HUSB Structures --- p.127 / Chapter E --- Primitive minimal 4-way global routing Structures --- p.132

This thesis focuses on implementing radio frequency (rf) reflectometry techniques for dispersive detection of charge and spin dynamics in nanoscale devices. I have investigated three aspects of rf reflectometry using state-of-the-art silicon (Si) complementary metal-oxide-semiconductor (CMOS) nanowire field effect transistors (NWFETs). First, a high-sensitivity capacitive gate-based charge sensor is developed by optimising the external matching circuit to detect capacitive changes in the high frequency resonator. A new circuit topology is used where superconducting niobium nitride (NbN) inductor is connected in parallel with a single-gate Si NWFET resulting in resonators with loaded Q-factors in the 400-800 range. For a resonator operating at 330 MHz, I have achieved a charge sensitivity of 7.7 $\mu e/\sqrt{\text{Hz}}$ and, when operating at 616 MHz, I get 1.3 $\mu e/\sqrt{\text{Hz}}$. This gate-based sensor can be used for fast, accurate and scalable techniques for quantum state readout in Si CMOS based quantum computing. Second, this new circuit topology for the resonator is used with a dual-gate Si NWFET. This dual-gate device geometry provides access to a double quantum dot (DQD) system in few electron regime. The spin-state of the two-electron DQD system is detected dispersively using Pauli spin blockade between joint singlet S(2,0) and triplet T$_-$(1,1) states in a finite magnetic field $B$. The singlet-triplet relaxation time $T_1$ at $B=4.5$~T is measured to be $\sim$1 ms using standard homodyne detection technique. Third, I expand the range of applications of gate-based sensing to accurate temperature measurements. I have experimentally demonstrated a primary thermometer by embedding a single-gate Si NWFET with the rf capacitive gate-based sensor. The thermometer, termed as gate-based electron thermometer (GET), relies on cyclic electron tunneling between discrete energy levels of a quantum dot and a single electron reservoir in the NWFET. I have found that the full-width-half-maximum (FWHM) of the resonator phase response depends linearly with temperature via well known physical law by using the ratio $k_\text{B}/e$ between the Boltzmann constant and the electron charge. The GET is also found to be magnetic field independent like other primary thermometers such as Coulomb blockade and shot noise thermometers.

Depuis sa découverte, les propriétés électroniques exceptionnelles du graphène ont fait l'objet d'un nombre impressionnant d'études, faisant émerger un nouveau domaine de recherche autour des cristaux bidimensionnels. La spectroscopie Raman permet d'accéder de façon rapide, non destructive et sélective en symétrie, à la dynamique des électrons et à leur couplage avec les autres degrés de liberté d'un matériau. Jusqu'au présent, cependant, cette technique a été réservée presque exclusivement à la caractérisation des propriétés vibrationnelles du graphène, qui ne sondent qu'indirectement ses propriétés électroniques. Dans ce travail je mets en évidence le signal Raman électronique de mono- et multi-couches de graphène en le modulant avec une tension de grille. Pour cela j'ai combiné des techniques avancées de fabrication de dispositifs avec un microscope Raman spécialement conçu pour cet objectif. Grâce à l'effet du champ électrique, le continuum Raman électronique du graphène dû aux transitions inter-bande à travers le cône de Dirac, a été identifié et son intensité quantifiée pour la première fois. Les spectres, avec la présence d'un blocage de Pauli des excitations électroniques, sont en excellent accord avec les prévisions théoriques. Les mesures résolues en polarisation ont mis en évidence une propriété originale de la spectroscopie Raman: le fait d'être une sonde privilégiée des excitations électroniques chirales. Cette propriété, attribuée à un phénomène d'interférences quantiques entre les amplitudes de diffusion, ouvre des prospectives très intéressantes dans l'étude d'autres cristaux bidimensionnels et des phases topologiques / Since its discovery, the exceptional electronic properties of graphene have been studied in an impressive number of academic works, giving birth to a new research field dealing with two-dimensional crystals. Raman spectroscopy is a quick, non-destructive and symmetry-selective way to probe the dynamics of electrons and to their coupling with the other degrees of freedom of a material. Until now, nonetheless, this technique had been almost exclusively reserved to the characterization of graphene's vibrational properties, which probe its electronic properties only indirectly. In this work I unravel the electronic Raman signal of mono- and multi-layer graphene tuning it with a gate voltage. In order to do so, I combined advanced techniques of device fabrication with a Raman microscope specifically designed for this goal. By means of the electric field effect, I identified and quantified for the first time the intensity of the electronic Raman continuum of graphene due to the inter-band transitions through the Dirac cone. The spectra, with the presence of a Pauli blocking of electronic excitations, match perfectly with theoretical expectations. The polarization resolved measurements revealed an original property of Raman spectroscopy: it is a unique probe of chiral electronic excitations. This property, attributed to a quantum interferences phenomenon between scattering amplitudes, opens very interesting perspectives in the study of other two-dimensional crystals and of topological phases

This explorative research examines a contemporary representation for suicide. Utilizing a dualistic framework of biology and technology, I codify diverse theoretical discourses into why people commit suicide. My practical research then merges opposing binaries of 'fact' (the need to understand) within 'fiction' (the need to tell narratives). In context of this study a person who has taken their own life is the 'author' and the researcher is the 'reader' of this event ‐ I investigate how the reader imposes their own narrative upon the author.

München, University der Bundeswehr, Diss., 2005.

The motivation to study this non-classical CMOS device is necessary to face with the ITRS constraints. In the ITRS roadmap, the gate length of devices are being scaled down rapidly but this rapid scaling is not in pace with the relatively slow scaling of the gate equivalent oxide thickness which leads to a degradation in the performance of the transistor. One of the solutions to this problem is the use of non-classical devices, such as the Gate-All-Around (GAA) MOSFET. Owing to the flexibility of SOI technology, these novel devices can be adapted to this technology bringing along with it the benefit of SOI technology. One of the main advantage of building this GAA device on SOI technology is that it offers the possibility whereby the second gate is easily built into the back of the device. GAA devices are also interesting because they do not need to scale down the thickness of the gate oxide rapidly but still able to maintain a suitable thickness to avoid problems such as current leakage through the thin gate oxide by tunnelling. The objective of this research can be divided into three parts; the first is to study the feasibility of the various fabrication process for this GAA device, the second to analyse the electrical characteristics of these fabricated GAA devices from DC characteristics up to 110 GHz and the third one is the use of commercial numerical simulation softwares (IE3D, Silvaco) in order to describe the physics of these novel devices. In this study, these different structures shows advantages and disadvantages when used in either analog or RF applications. The graded-channel structure has shown that it is advantageous when used in high performance analog circuits. The advantages of this structure is further enhanced when it is combined with the double-gate structure, forming a double-gate graded channel SOI MOSFET. Optimizing in terms of doping level along the channel of the graded-channel is important to yield good electrical results. In order for these devices to be successful commercially, it is important that they are compatible with the fabrication technology and trends available today and in the near future. To confirm that these devices can be adapted into today's and tomorrow's technology, we have shown that these they are easily adaptable in the current technology. Multiple-gate devices are a new group of devices which have been identified by ITRS as potential devices to meet the demands in the future. In this study, we have shown that these multiple-gate devices do indeed show improved short-channel effects and improved analog and RF characteristics when compared to the single-gate devices in existence. One of the main contributors to these improvements is due to what is known as the “volume inversion”.

Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2006. / Includes bibliographical references (p. 63-71).