Thesis (Ph. D.)--University of California, Riverside, 2008. / Includes abstract. Title from first page of PDF file (viewed March 8, 2010). Available via ProQuest Digital Dissertations. Includes bibliographical references (p. 150-168). Also issued in print.

Thesis (Ph. D.)--University of Texas at Austin, 2002. / Vita. Includes bibliographical references. Available also from UMI Company.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, December 2003. / Thesis advisor(s): Herschel H. Loomis, Jr., Alan A. Ross. Includes bibliographical references (p. 241-243). Also available online.

Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010. / Committee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Ghovanloo, Maysam. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Thesis (M.S.)--Brigham Young University. Dept. of Electrical and Computer Engineering, 2003. / Includes bibliographical references (p. 229-232).

Thesis--Auburn University, 2010. / Abstract. Includes bibliographic references (p.162-167).

Ultra-deep submicron circuits require accurate modeling of gate delay in order to meetaggressive timing constraints. With the lack of statistical data, variability due to the mechanical manufacturing process and its chemical properties poses a challenging problem. Discrete gate sizing requires (i) accurate models that take into account random parametric variation and (ii) a fair allocation of resources to optimize the solution. The proposed GTFUZZ gate sizing algorithm handles both tasks. Gate sizing is modeled as a resource allocation problem using fuzzy game theory. Delay is modeled as a constraint and power is optimized in this algorithm. In GTFUZZ, delay is modeled as a fuzzy goal with fuzzy parameters to capture the imprecision of gate delay early in the design phase when extensive empirical data is absent. Dynamic power is modeled as a fuzzy goal without varying coefficients. The fuzzy goals provide a flexible platform for multimetric optimization. The robust GTFUZZ algorithm is compared against fuzzy linear programming (FLP) and deterministic worst-case FLP (DWCFLP) algorithms. The benchmark circuits are first synthesized, placed, routed, and optimized for performance using the Synopsys University 32/28nm standard cell library and technology files. Operating at the optimized clock frequency, results show an average power reduction of about 20% versus DWCFLP and 9% against variation-aware gate sizing with FLP. Timing and timing yield are verified by both Synopsys PrimeTime and Monte Carlo simulations of the critical paths using HSPICE.

To overcome the issues of mobility degradation and charge trapping in silicon high-κ MOSFET, a stacked Y₂O₃(top)/HfO2(bottom) gate dielectric on silicon substrate has been developed. Compared to the HfO₂ reference, the new dielectric shows similar scalability, but superior channel mobility and device reliability. The mobility improvement can be attributed to reduced remote phonon scattering, which is associated with the smaller ionic polarization of Y₂O₃, and the suppressed coulomb scattering due to less electron trapping in the bulk of high-κ layer, and reduced metal impurities in the substrate. The passivation mechanisms for the silicon IPL passivation technique in GaAs/[alpha]-Si IPL/high-κ MOS system have been investigated. We demonstrate the [alpha]-Si IPL thickness dependence and substrate type dependence of interface state density (Dit) for GaAs MOS capacitors. The interface state density is strongly correlated to the thickness and quality of un-oxidized Si IPL and its interaction with the underlying substrate. The results can be explained by the models related to the quantum well narrowing or the reduced local trap density as the unoxidized Si IPL layer thickness decreases. By using optimal Si IPL thickness (~10 Å), GaAs MOS devices can achieve the same interface quality, as its silicon counterpart. Using Si IPL to unpin the surface Fermi level, the selfaligned depletion-mode and enhancement-mode GaAs n-MOSFETs are demonstrated. In addition, the charge trapping and wear-out characteristics of the GaAs/Si IPL/HfO2/TaN MOS devices are systematically investigated. High performance In0.53Ga0.47As nMOSFETs with Si IPL and HfO2 gate oxide have been demonstrated. We systematically investigate the impacts of 1) Source/Drain activation temperature, 2) post deposition annealing (PDA) temperature, 3) In[subscrip 0.53]Ga[subscript 0.47]As channel doping concentration, 4) channel thickness and 5) Si IPL thickness on the transistor performances. With the [mu]m, V[subscript d]=50 mV), drive current of 158 mA/mm (L[subscript g]=5 [mu]m, V[subscript gs]=V[subscript th]+2 V, V[subscript d]=2.5 V), and the peak effective channel mobility of 1034 cm2/V-s. InP nMOSFETs with Si IPL and HfO₂ have been demonstrated. The effects of Si IPL on the transistor performances and reliability characteristics are investigated. It is found that even through InP is a forgiving channel material with respect to surface Fermi level pinning, applying silicon IPL still improves the transistor performance and reliability. But the choice of Si IPL is critical for device design. Both in-sufficient passivation and excessive Si IPL should be avoided. optimal combination of these impacting factors, excellent device characteristics have been obtained, including the peak transconductance of 7.7 mS/mm (Lg=5 μm, Vd=50 mV), drive current of 158 mA/mm (Lg=5 [mu]m, Vgs=Vth+2 V, Vd=2.5 V), and the peak effective channel mobility of 1034 cm2/V-s. InP nMOSFETs with Si IPL and HfO₂ have been demonstrated. The effects of Si IPL on the transistor performances and reliability characteristics are investigated. It is found that even through InP is a forgiving channel material with respect to surface Fermi level pinning, applying silicon IPL still improves the transistor performance and reliability. But the choice of Si IPL is critical for device design. Both in-sufficient passivation and excessive Si IPL should be avoided. / text

This thesis revolves around product development in a medium-sized Swedish company. The company in question is called S:t Erik and manufactures a wide range of products made out of concrete and operates in several locations in Sweden. The study has been carried out during 20 weeks with a starting point in January, year 2015. The goal of the study is to deliver a directly implementable development process that support the company's vision and aim towards a more reliable and resource-saving product development process. The study has been conducted through interviews with people directly involved in the product development process. In addition to the interviews, an observational study carried out in the company's production unit in Uppsala and a benchmarking at S:t Eriks plant in Staffanstorp. Which though co-examination with theory revolving the Stage gate process formed the basis for the developed proposals for improvement. To achieve a more accurate product development S:t Erik is recommended to work with its product development on a project basis with clear guidance in the form of a dedicated project manager in combination with a standardized development procedure. Through a proposed model including the work guidelines and though structured development phases S:t Eriks is presented with the opportunity to drastically decrease the risk involved with the company’s product development. The result also includes a proposal to carry out the proposed working model through the online feature in Word, in response to discovered problems revolving communication, access to information and transfer of knowledge. To ensure that S:t Erik is able to interpret and meet the expressed customer need, and at the same time simplify the internal communication they are recommended to incorporate a 3D printer in the early stages of the product development. For additional ways to meet customer needs a concept collection folder available for quick and easy collection of ideas and suggestions online or alternatively on the company intranet is suggested. Finally a procedure for how the working model could be used in practise is presented in an effort to archive a successful implementation at S:t Eriks.

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