Recently, there is great interest in achieving higher-level integration, higher data rates, and reduced overall costs. At millimeter-wave (mm-wave) bands, the wavelength is small enough to realize an antenna-on-chip (AoC), which is an ideal solution for high compactness and lower costs. However, the main drawback of AoC is the low resistivity (10 Ω-cm) Si substrate used in the standard CMOS technology, which absorbs most radio-frequency (RF) power that was supposed to be radiated by the on-chip antenna. Moreover, due to the high relative permittivity (11.9) and relatively large electrical thickness of the Si, higher order surface wave modes get excited, which further degrade the antenna radiation performance. In order to alleviate the above-mentioned issues with the low gain of AoC, a combination of an artificial magnetic conductor (AMC) surface, a high dielectric constant superstrate, and a Fresnel lens is presented in this work. The AMC is realized in standard CMOS technology along with the AoC, whereas the superstrate and lens are part of a smart packaging solution. The AMC surface can change wave propagation characteristics at the operating frequency to achieve in-phase reflection, resulting in gain enhancement by reducing the loss in the substrate. The high dielectric constant superstrate behaves as an impedance transformer between the Si substrate and air, thus enhancing the coupling to air. Finally, the Fresnel lens enhances the gain by focusing the electromagnetic (EM) radiation beam at the boresight. For AoC realization, a standard 0.18 μm CMOS process was utilized. A coplanar waveguide (CPW) fed monopole on-chip antenna at 71 GHz, along with the corresponding driving circuit, was designed and fabricated. The AMC enhances the gain by 3 dB. Since the chip needs to be packaged anyways, in this work, we optimize the package to provide further gain enhancement. This smart package, comprising a superstrate and a Fresnel lens, provides a gain enhancement of 16 dB. The overall combination of the optimized AMC surface, superstrate layer, and lens package can provide a gain enhancement of around 19 dB. Furthermore, the package has been realized through additive manufacturing techniques that ensure lower costs for the overall system.

This dissertation develops design methods and architectures which allow analog circuits to operate at VT + 2Vds,sat, the minimum supply for CMOS circuits with all transistors in the active region where Vds,sat is the drain to source saturation voltage of a MOS transistor. Techniques which meet this criteria for rail-to-rail input stages, gain enhancement stages, and output stages are discussed and developed. These techniques are used to design four fully-differential rail-to-rail amplifiers. The highest gain is shown to be attained using a drain voltage equalization (DVE) or active-bootstrapping technique which produces more than 100dB of gain in a two stage amplifier with a bulk-driven input pair while showing no bandwidth degradation when compared to amplifier architectures with similar biasing. The low voltage design techniques are extended to switching and sampling circuits. A 10-bit digital to analog converter (DAC) and a 10-bit analog to digital converter (ADC) are designed and fabricated in a 0.35um dual-well CMOS process to prove the developed design methods, architectures, and techniques. The 10-bit DAC operates at 1MSPS with near rail-to-rail differential output operation with a 700mV supply voltage. This supply voltage, which is 150mV lower than the VT+2Vds,sat limit, is attained by using a bulk driven threshold voltage lowering technique. The ADC design is a fully-differential pipelined 10-bit converter that operates at 500kSPS with a full scale input range equal to the supply voltage and can operate at supply voltages as low as 650mV, 200mV below the VT + 2Vds,sat limit. The design methods and architectures can be used in advanced processes to maintain gain and minimize supply voltage. These designs show a minimum supply improvement over previously published designs and prove the efficacy of the design architectures and techniques presented in this dissertation.

Yes / In this paper, a pyramidal horn antenna loaded with unit cell of metamaterial is proposed, designed and realized for L-band that including terrestrial digital audio broadcasting TDAB, GPS and GSM. The proposed antenna operates in the frequency range from 1.722 GHz to 1.931 GHz. The metamaterial is fabricated on a printed circuit board as Capacitive Loaded Loop (CLL). The work aims to exhibit the advantage of metamaterial loaded inside the horn antenna in terms of the gain enhancement of the radiation pattern and the resonant frequency shift towards lower frequency. The retrieval technique used show that the constitutive parameters of the unit cell as CLL have a zero index metamaterial (ZIM) from 1.34 GHz to 1.49 GHz and a near zero index of refraction from 1.495 GHz to 2 GHz, which is within the operating frequency of the horn antenna. The achieved results show that the total gain is improved over the frequency range. The simulation and the measurement are in good agreement.

Yes / A Novel design of a curved single-layered frequency selective surface with an 11 × 11 array of a 13 × 13 mm-sized unit cell has been merged with a miniaturized, CPW-fed ultra-wideband monopole of dimensions (20 × 25 mm2) for gain enhancement. The suggested prototype, crafted on an FR-4 dielectric substrate and demonstrates a very broad bandwidth starting from 2.66 to 17.98 GHz (148%), which covers the entire UWB frequency band. The combined antenna-curved FSS reflector shows a very important gain improvement from 0.2–5.4 dB to 8.8–14.9 dB, having a peak gain increase of 10 dB at 10.6 GHz. Basic design features were studied and discussed through simulations, yielding promising results The proposed structure can be used in UWB and GPR applications. / The full-text of this article will be released for public view at the end of the publisher embargo on 31 Oct 2024.

abstract: As wireless communication enters smartphone era, more complicated communication technologies are being used to transmit higher data rate. Power amplifier (PA) has to work in back-off region, while this inevitably reduces battery life for cellphones. Various techniques have been reported to increase PA efficiency, such as envelope elimination and restoration (EER) and envelope tracking (ET). However, state of the art ET supply modulators failed to address high efficiency, high slew rate, and accurate tracking concurrently. In this dissertation, a linear-switch mode hybrid ET supply modulator utilizing adaptive biasing and gain enhanced current mirror operational transconductance amplifier (OTA) with class-AB output stage in parallel with a switching regulator is presented. In comparison to a conventional OTA design with similar quiescent current consumption, proposed approach improves positive and negative slew rate from 50 V/µs to 93.4 V/µs and -87 V/µs to -152.5 V/µs respectively, dc gain from 45 dB to 67 dB while consuming same amount of quiescent current. The proposed hybrid supply modulator achieves 83% peak efficiency, power added efficiency (PAE) of 42.3% at 26.2 dBm for a 10 MHz 7.24 dB peak-to-average power ratio (PAPR) LTE signal and improves PAE by 8% at 6 dB back off from 26.2 dBm power amplifier (PA) output power with respect to fixed supply. With a 10 MHz 7.24 dB PAPR QPSK LTE signal the ET PA system achieves adjacent channel leakage ratio (ACLR) of -37.7 dBc and error vector magnitude (EVM) of 4.5% at 26.2 dBm PA output power, while with a 10 MHz 8.15 dB PAPR 64QAM LTE signal the ET PA system achieves ACLR of -35.6 dBc and EVM of 6% at 26 dBm PA output power without digital pre-distortion (DPD). The proposed supply modulator core circuit occupies 1.1 mm2 die area, and is fabricated in a 0.18 µm CMOS technology. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

Yes / The paper demonstrates an effective technique to significantly enhance the bandwidth and radiation gain of an otherwise narrowband composite right/left-handed transmission-line (CRLH-TL) antenna using a non-Foster impedance matching circuit (NF-IMC) without affecting the antenna's stability. This is achieved by using the negative reactance of the NF-IMC to counteract the input capacitance of the antenna. Series capacitance of the CRLH-TL unit-cell is created by etching a dielectric spiral slot inside a rectangular microstrip patch that is grounded through a spiraled microstrip inductance. The overall size of the antenna, including the NF-IMC at its lowest operating frequency is 0.335λ0 × 0.137λ0 × 0.003λ0, where λ0 is the free-space wavelength at 1.4 GHz. The performance of the antenna was verified through actual measurements. The stable bandwidth of the antenna for |S11|≤ - 18 dB is greater than 1 GHz (1.4-2.45 GHz), which is significantly wider than the CRLH-TL antenna without the proposed impedance matching circuit. In addition, with the proposed technique the measured radiation gain and efficiency of the antenna are increased on average by 3.2 dBi and 31.5% over the operating frequency band. / This work is partially supported by RTI2018-095499-B-C31, Funded by Ministerio de Ciencia, Innovación y Universidades, Gobierno de España (MCIU/AEI/FEDER,UE), and innovation programme under grant agreement H2020-MSCA-ITN-2016 SECRET-722424 and the financial support from the UK Engineering and Physical Sciences Research Council (EPSRC) under grant EP/E022936/1.