Les propriétés électriques et mécaniques exceptionnelles du graphène font de ce matériau bidimensionnel à base de carbone, l’un des matériaux phare de la micro-électronique. L’objectif des ces travaux de recherche est de démontrer les possibilités nouvelles offertes par le graphène dans le domaine des transistors ultra-rapides et faible bruit. La fabrication de transistors RF a été réalisée sur des échantillons obtenus par graphitisation de substrat SiC. Ce travail s’est déroulé dans le cadre du projet ANR MIGRAQUEL, en partenariat avec le Laboratoire de Photonique et de Nanostructures (LPN), le Laboratoire Pierre Aigrain (LPA) de l’ENS, et l’Institut d’Electronique Fondamentale (IEF). Les couches de graphène utilisées dans cette thèse ont été synthétisées au LPN. Le développement et l’optimisation des différents procédés technologiques se sont déroulés en salle blanche. Les propriétés du matériau tels que la mobilité, la résistance par carré, ainsi que certaines caractéristiques technologiques comme les résistances de contact sont déduites de structures spécifiques. Ensuite, des caractérisations électriques en régime statique et dynamique effectuées sur des transistors graphène à effet de champ (GFET) ont été effectuées. Les meilleures performances hyperfréquence ont été obtenues sur des transistors à base de nano-rubans de graphène (GNRFET), avec une fréquence de coupure « intrinsèque » du gain en courant ft_intr=50GHz et une fréquence maximale d’oscillation fmax=29GHz; et ce pour une longueur de grille de Lg=75nm à Vds=300mV. / Outstanding electrical and mechanical properties of graphene make this two-dimensional carbon-based material, one of the leading microelectronics materials. The aim of this thesis is to demonstrate the new possibilities offered by graphene in the field of high-speed and low-noise transistors. RF transistors have been produced on samples obtained by graphitization of SiC substrates. This was possible through the ANR program MIGRAQUEL in partnership with the Laboratory of Photonics and Nanostructures (LPN), the Pierre Aigrain Laboratory (LPA) of ENS and the Institute of Fundamental Electronics (IEF). Graphene samples used in this thesis were synthesized in LPN. The development and optimization of the different technological steps process took place in clean-rooms. Material properties such as mobility, sheet resistance and some technological parameters such as contact resistance are made using specific samples. Then, each GFET and GNRFET (Graphene Nano-Ribbons FET) transistor were analyzed both in static and high-frequency regime. Finally, the best RF measurement in terms of intrinsisc current gain cut-off frequency and maximum oscillation frequency are respectively fr_intr=50GHz and fmax=29GHz; for a gate length of Lg=75nm at Vds=300mV.

Indiana University-Purdue University Indianapolis (IUPUI) / As the search for ever-higher-speed, greater-density, and lower-power technologies accelerates, so does the quest for devices and methodologies to fulfill the increasingly-difficult requirements for these technologies. A possible means by which this may be accomplished is to utilize superconducting devices and graphene nanoribbon nanotechnologies. This is because superconductors are ultra-low-power devices capable of generating extremely high frequency (EHF) signals, and graphene nanoribbons are nanoscale devices capable of extremely high-speed and low-power signal amplification due to their high-mobility/low-resistance channels and geometry-dependent bandgap structure. While such a hybrid co-integrated system seems possible, no process by which this may be accomplished has yet been proposed. In this thesis, the system limitations are explored in-depth, and several possible means by which superconducting and graphene nanotechnological systems may be united are proposed, with the focus being placed on the simplest method by which the technologies may be hybridized and integrated together, while maintaining control over the intended system behavior. This is accomplished in three parts. First, via circuit-level simulation, a semi-optimized, low-power (~0.21 mW/stage) graphene-based amplifier is developed using ideal and simplified transmission line properties. This system is theoretically capable of 159-269 GHz bandwidth with a Stern stability K >> 1 and low noise figure 2.97 <= F <= 4.33 dB for all appropriate frequencies at temperatures between 77 and 90 K. Second, an investigation of the behavior of several types of possible interconnect methodologies is performed, utilizing hybrid substrates and material interfaces/junctions, demonstrating that an Ohmic-contact superconducting-normal transmission line is optimal for a hybrid system with self-reflections at less than -25 dB over an operating range of 300 GHz. Finally, a unified layout and lithography construction process is proposed by which such a hybrid system could be developed in a monolithic physical system on a hybrid substrate while maintaining material and layout integrity under varying process temperatures.

Indiana University-Purdue University Indianapolis (IUPUI) / Recent ULSI (ultra large scale integration) technology emphasizes small size devices, featuring low power and high switching speed. Moore's law has been followed successfully in scaling down the silicon device in order to enhance the level of integration with high performances until conventional devices failed to cop up with further scaling due to limitations with ballistic effects, and challenges with accommodating dopant fluctuation, mobility degradation, among other device parameters. Recently, Graphene based devices o ered alternative approach, featuring small size and high performances. This includes high carrier mobility, high carrier density, high robustness, and high thermal conductivity. These unique characteristics made the Graphene devices attractive for high speed electronic architectures. In this research, Graphene devices were integrated into applications with analog, digital, and mixed signals based systems. Graphene devices were briefly explored in electronics applications since its first model developed by the University of Illinois, Champaign in 2013. This study emphasizes the validation of the model in various applications with analog, digital, and mixed signals. At the analog level, the model was used for voltage and power amplifiers; classes A, B, and AB. At the digital level, the device model was validated within the universal gates, adders, multipliers, subtractors, multiplexers, demultiplexers, encoders, and comparators. The study was also extended to include Graphene devices for serializers, the digital systems incorporated into the data structure storage. At the mixed signal level, the device model was validated for the DACs/ADCs. In all components, the features of the new devices were emphasized as compared with the existing silicon technology. The system functionality and dynamic performances were also elaborated. The study also covered the linearity characteristics of the devices within full input range operation. GNRFETs with a minimum channel length of 10nm and an input voltage 0.7V were considered in the study. An electronic design platform ADS (Advanced Design Systems) was used in the simulations. The power amplifiers showed noise figure as low as 0.064dbs for class A, and 0.32 dbs for class B, and 0.69 dbs for class AB power amplifiers. The design was stable and as high as 5.12 for class A, 1.02 for class B, and 1.014 for class AB. The stability factor was estimated at 2GHz operation. The harmonics were as low as -100 dbs for class A, -60 dbs for class B, and -50dbs for class AB, all simulated at 1GHz. The device was incorporated into ADC system, and as low as 24.5 micro Watt power consumption and 40 nsec rise time were observed. Likewise, the DAC showed low power consumption as of 4.51 micro Watt. The serializer showed as minimum power consumption of the order of 0.4mW. These results showed that these nanoscale devices have potential future for high-speed communication systems, medical devices, computer architecture and dynamic Nano electromechanical (NEMS) which provides ultra-level of integration, incorporating embedded and IoT devices supporting this technology. Results of analog and digital components showed superiority over other silicon transistor technologies in their ultra-low power consumption and high switching speed.

Recent ULSI (ultra large scale integration) technology emphasizes small size devices, featuring low power and high switching speed. Moore's law has been followed<br>successfully in scaling down the silicon device in order to enhance the level of integration with high performances until conventional devices failed to cop up with further scaling due to limitations with ballistic effects, and challenges with accommodating dopant fluctuation, mobility degradation, among other device parameters. Recently, Graphene based devices offered alternative approach, featuring small size<br>and high performances. This includes high carrier mobility, high carrier density, high robustness, and high thermal conductivity. These unique characteristics made the<br>Graphene devices attractive for high speed electronic architectures. In this research, Graphene devices were integrated into applications with analog, digital, and mixed<br>signals based systems.<br>Graphene devices were briefly explored in electronics applications since its first model developed by the University of Illinois, Champaign in 2013. This study emphasizes the validation of the model in various applications with analog, digital, and mixed signals. At the analog level, the model was used for voltage and power amplifiers; classes A, B, and AB. At the digital level, the device model was validated within the universal gates, adders, multipliers, subtractors, multiplexers, demultiplexers, encoders, and comparators. The study was also extended to include Graphene devices<br><div>for serializers, the digital systems incorporated into the data structure storage. At the mixed signal level, the device model was validated for the DACs/ADCs. In all components, the features of the new devices were emphasized as compared with the existing silicon technology. The system functionality and dynamic performances were also elaborated. The study also covered the linearity characteristics of the devices within full input range operation.</div><div>GNRFETs with a minimum channel length of 10nm and an input voltage 0.7V were considered in the study. An electronic design platform ADS (Advanced Design<br>Systems) was used in the simulations. The power amplifiers showed noise figure as low as 0.064dbs for class A, and 0.32 dbs for class B, and 0.69 dbs for class AB power<br>amplifiers. The design was stable and as high as 5.12 for class A, 1.02 for class B, and 1.014 for class AB. The stability factor was estimated at 2GHz operation. The harmonics were as low as -100 dbs for class A, -60 dbs for class B, and -50dbs for class AB, all simulated at 1GHz. The device was incorporated into ADC system, and as<br>low as 24.5 micro Watt power consumption and 40 nsec rise time were observed. Likewise, the DAC showed low power consumption as of 4.51 micro Watt. The serializer showed as minimum power consumption of the order of 0.4mW. <br></div><div>These results showed that these nanoscale devices have potential future for high-speed communication systems, medical devices, computer architecture and dynamic<br>Nano electromechanical (NEMS) which provides ultra-level of integration, incorporating embedded and IoT devices supporting this technology. Results of analog and<br>digital components showed superiority over other silicon transistor technologies in their ultra-low power consumption and high switching speed.<br></div><div><br></div>

Like cell to the human body, transistors are the basic building blocks of any electronics circuits. Silicon has been the industries obvious choice for making transistors. Transistors with large size occupy large chip area, consume lots of power and the number of functionalities will be limited due to area constraints. Thus to make the devices smaller, smarter and faster, the transistors are aggressively scaled down in each generation. Moore's law states that the transistors count in any electronic circuits doubles every 18 months. Following this Moore's law, the transistor has already been scaled down to 14 nm. However there are limitations to how much further these transistors can be scaled down. Particularly below 10 nm, these silicon based transistors hit the fundamental limits like loss of gate control, high leakage and various other short channel effects. Thus it is not possible to favor the silicon transistors for future electronics applications. As a result, the research has shifted to new device concepts and device materials alternative to silicon. Carbon is the next abundant element found in the Earth and one of such carbon based nanomaterial is graphene. Graphene when extracted from Graphite, the same material used as the lid in pencil, have a tremendous potential to take future electronics devices to new heights in terms of size, cost and efficiency. Thus after its first experimental discovery of graphene in 2004, graphene has been the leading research area for both academics as well as industries. This dissertation is focused on the analysis and optimization of graphene based circuits for future electronics. The first part of this dissertation considers graphene based transistors for analog/radio frequency (RF) circuits. In this section, a dual gate Graphene Field Effect Transistor (GFET) is considered to build the case study circuits like voltage controlled oscillator (VCO) and low noise amplifier (LNA). The behavioral model of the transistor is modeled in different tools: well accepted EDA (electronic design automation) and a non-EDA based tool i.e. \simscape. This section of the dissertation addresses the application of non-EDA based concepts for the analysis of new device concepts, taking LC-VCO and LNA as a case study circuits. The non-EDA based approach is very handy for a new device material when the concept is not matured and the model files are not readily available from the fab. The results matches very well with that of the EDA tools. The second part of the section considers application of multiswarm optimization (MSO) in an EDA tool to explore the design space for the design of LC-VCO. The VCO provides an oscillation frequency at 2.85 GHz, with phase noise of less than -80 dBc/Hz and power dissipation less than 16 mW. The second part of this dissertation considers graphene nanotube field effect transistors (GNRFET) for the application of digital domain. As a case study, static random access memory (SRAM) hs been design and the results shows a very promising future for GNRFET based SRAM as compared to silicon based transistor SRAM. The power comparison between the two shows that GNRFET based SRAM are 93% more power efficient than the silicon transistor based SRAM at 45 nm. In summary, the dissertation is to expected to aid the state of the art in following ways: 1) A non-EDA based tool has been used to characterize the device and measure the circuit performance. The results well matches to that obtained from the EDA tools. This tool becomes very handy for new device concepts when the simulation needs to be fast and accuracy can be tradeoff with. 2)Since an analog domain lacks well-design design paradigm, as compared to digital domain, this dissertation considers case study circuits to design the circuits and apply optimization. 3) Performance comparison of GNRFET based SRAM to the conventional silicon based SRAM shows that with maturation of the fabrication technology, graphene can be very useful for digital circuits as well.