Les architectures mixtes contenant des composants programmables et d'autres reconfigurables peuvent fournir les performances de calcul nécessaires pour satisfaire les contraintes imposées aux applications temps réel. Mais l'implantation et d'optimisation de ces applications temps réel sur ce type d'architectures est une tâche complexe qui prend un temps énorme. Dans ce contexte, nous proposons un outil de prototypage rapide visant ce type d'architectures. Cet outil se base sur une extension que nous proposons de la méthodologie Adéquation Algorithme Architecture (AAA). Il permet d'effectuer automatiquement le partitionnement et l'ordonnancement optimisés des opérations de l'application sur les composants de l'architecture cible et la génération automatique des codes correspondants. Nous avons utilisé cet outil pour l'implantation de l'estimateur de mouvement de la norme H.264/AVC sur une architecture composée d'un processeur NIOS II d'Altera et d'un FPGA Stratix III. Ainsi nous avons pu vérifier le bon fonctionnement de notre outil et validé notre générateur automatique de code mixte / Mixed architectures containing programmable devices and reconfigurable ones can provide calculation performance necessary to meet constraints of real-time applications. But the implementation and optimization of these applications on this kind of architectures is a complex task that takes a lot of time. In this context, we propose a rapid prototyping tool for this type of architectures. This tool is based on our extension of the Adequacy Algorithm Architecture methodology (AAA). It allows to automatically perform optimized partitioning and scheduling of the application operations on the target architecture components and generation of correspondent codes. We used this tool for the implementation of the motion estimator of the H.264/AVC on an architecture composed of a Nios II processor and Altera Stratix III FPGA. So we were able to verify the correct running of our tool and validate our automatic generator of mixed code

H.264/AVC yra pagrįstas tradicinėmis vaizdo kodavimo sąvokomis, bet palyginti su ankstesniais standartais, su svarbiais tam tikrais skirtumais.Reikšmingiausi skirtumai yra padidintas judėjimo apskaičiavimo pajėgumas, mažas bloko dydis su tikslia transformacija, adaptyvus blokų mažinimo filtras ir patobulinti entropijos kodavimo metodai. palygintų su MPEG-2. H.264/AVC pasiekia daugiau kaip 50 procentų, kodavimo prieaugį palyginus su MPEG-2 visuose PSNR situacijose. H.264/AVC standartas dirba žymiai geriau už visus ankstesnius standartus, dėl padidėjusio kodavimo lankstumo ir sudėtingumo. / Video coding is the entire process of compressing and decompressing of a digital video signal. Then the mainstream video compression tools developed in the past several years by both Video Coding Experts Group (VCEG) and Moving Picture Experts Group (MPEG) are briefly introduced. Since its invention from early 1990 modern digital video compression techniques have played an important role in the world of telecommunication and multimedia systems where bandwidth is still a valuable commodity. Evolution from the early MPEG-1/H.261 to the current H.264/AVC video codec gradually improves the coding efficiency at the cost of design complexity. Compared with its prior standards the H.264/AVC is able to achieve nearly doubled coding gain, while the encoder's and decoder's complexity increase 5 – 10 and 2 – 3 times respectively.

Les architectures mixtes contenant des composants programmables et d'autres reconfigurables peuvent fournir les performances de calcul nécessaires pour satisfaire les contraintes imposées aux applications temps réel. Mais l'implantation et d'optimisation de ces applications temps réel sur ce type d'architectures est une tâche complexe qui prend un temps énorme. Dans ce contexte, nous proposons un outil de prototypage rapide visant ce type d'architectures. Cet outil se base sur une extension que nous proposons de la méthodologie Adéquation Algorithme Architecture (AAA). Il permet d'effectuer automatiquement le partitionnement et l'ordonnancement optimisés des opérations de l'application sur les composants de l'architecture cible et la génération automatique des codes correspondants. Nous avons utilisé cet outil pour l'implantation de l'estimateur de mouvement de la norme H.264/AVC sur une architecture composée d'un processeur NIOS II d'Altera et d'un FPGA Stratix III. Ainsi nous avons pu vérifier le bon fonctionnement de notre outil et validé notre générateur automatique de code mixte / Mixed architectures containing programmable devices and reconfigurable ones can provide calculation performance necessary to meet constraints of real-time applications. But the implementation and optimization of these applications on this kind of architectures is a complex task that takes a lot of time. In this context, we propose a rapid prototyping tool for this type of architectures. This tool is based on our extension of the Adequacy Algorithm Architecture methodology (AAA). It allows to automatically perform optimized partitioning and scheduling of the application operations on the target architecture components and generation of correspondent codes. We used this tool for the implementation of the motion estimator of the H.264/AVC on an architecture composed of a Nios II processor and Altera Stratix III FPGA. So we were able to verify the correct running of our tool and validate our automatic generator of mixed code

With the technological advancement, entertainment has become revolutionized and the High-definition (HD) video has become a common feature of our modern amusement devices. Moreover, the demand for wireless transmission of HD video is rising increasingly for its ubiquitous nature, easy installation and relocation. The high bandwidth requirement is the main concern for wireless transmission of high quality video streams. Research has been going on by the consumer electronics industry to provide different solutions of this issue, for the last few years.<p> In this research work, HD video transmission feasibility using the Ultra-wideband (UWB) communication channel is analyzed. The UWB channel is selected for its short-range, high-speed data transmission capability at low-cost, and low-power consumption. The maximum transmitting range of this technology is about 10 m at 100 Mbps data rate. Simulation is conducted by controlling key parameters, such as, in-loop deblocking filter, group of pictures, and quantization parameter of an H.264/AVC encoder. Here, standard HD video streams with different motion characteristics are used, and the impact of these parameters change on the reconstructed video quality and the broadcasting data rate are analyzed. Finally, a generalized parameters settings, and a video content dependent settings for an H.264/AVC encoder are proposed for different bandwidth requirements, as well as acceptable video quality. Performance evaluation of these parameters settings is performed, and the results are quite satisfactory as long as the symbol energy to noise power density ratio, Es/No, is above 15. With the proposed parameters settings, maximum 20 Mbps data rate is achieved with 33.5 dB Y-PSNR.

With the technological advancement, entertainment has become revolutionized and the High-definition (HD) video has become a common feature of our modern amusement devices. Moreover, the demand for wireless transmission of HD video is rising increasingly for its ubiquitous nature, easy installation and relocation. The high bandwidth requirement is the main concern for wireless transmission of high quality video streams. Research has been going on by the consumer electronics industry to provide different solutions of this issue, for the last few years.<p> In this research work, HD video transmission feasibility using the Ultra-wideband (UWB) communication channel is analyzed. The UWB channel is selected for its short-range, high-speed data transmission capability at low-cost, and low-power consumption. The maximum transmitting range of this technology is about 10 m at 100 Mbps data rate. Simulation is conducted by controlling key parameters, such as, in-loop deblocking filter, group of pictures, and quantization parameter of an H.264/AVC encoder. Here, standard HD video streams with different motion characteristics are used, and the impact of these parameters change on the reconstructed video quality and the broadcasting data rate are analyzed. Finally, a generalized parameters settings, and a video content dependent settings for an H.264/AVC encoder are proposed for different bandwidth requirements, as well as acceptable video quality. Performance evaluation of these parameters settings is performed, and the results are quite satisfactory as long as the symbol energy to noise power density ratio, Es/No, is above 15. With the proposed parameters settings, maximum 20 Mbps data rate is achieved with 33.5 dB Y-PSNR.

The intensive search of optimal matching block greatly increases the complexity of motion estimation that constitutes the most time-consuming part of H.264/AVC. This thesis presents a novel fast hierarchical motion search (FHMS) strategy along with a heuristic early termination technique. The proposed FHMS paradigm is based on the observation that most search operations can be avoided by sub-sampling current macroblocks first to reduce the dimensions of both reference pictures and search range. The early termination establishes a statistical threshold that makes motion search for stationary or quasi-stationary areas to terminate earlier without sacrificing accuracy. Experimental results show the proposed FHMS is highly time-efficient in finding the motion vectors and at the same time maintaining satisfactory video quality.

The H.264/AVC video coding standard aims to enable significantly improved compression performance compared to all existing video coding standards. For achieve this purpose, a robust rate-distortion optimization (RDO) [4] technique is employed to select the best coding mode and reference frame for each macro-block. As a result, the complexity and computation load increase drastically. This paper presents a fast mode decision algorithm for H.264/AVC inter-prediction based on frame difference. There used signal to noise ratio (SNR) of 4*4 block information based on adjustable threshold to judge the mode type. Experimental results show that the fast inter-prediction mode decision scheme increases the speed of motion estimation significantly with negligible loss of peak signal-to-noise ratio.

H.264/AVC is the latest international video coding standard. It was jointly developed by the Video Coding Experts Group (VCEG) of the ITU-T and the Moving Picture Experts Group (MPEG) of ISO/IEC. The goals of this standardization effort were enhanced compression efficiency and network friendly video representation. Because H.264 includes a lot of new characteristics and offers a lot of tools for compression, it can improve the quality of the compressed image greatly. H.264/AVC provides gains in compression efficiency of up to 50\% over a wide range of bit rates and video resolutions compared to previous standards. Object-based coding is the new feature that MPEG-4 supports. The object-based coding can reduce the region of motion estimation; this will increase the speed of coding. The output frame can be combined with the object-based coding sequence and also can be synthesized with the object-based coding sequence. Taking the advantage of the H.264/AVC and Object-based coding, the coding will be faster and the sequence will be smaller. In this thesis, we adopted the H.264/AVC video coding standard to implement the object coding.

H.264/AVC (Advance Video Coding) standard developed by ITU-T Video Coding Experts Group(VCEG) and ISO/IEC JTC1 Moving Picture Experts Group (MPEG), is one of the most powerful andcommonly used format for video compression. It is mostly used in internet streaming sources i.e.from media servers to end users. This Master thesis aims at designing a CODEC targeting the Baseline profile on FPGA.Uncompressed raw data is fed into the encoder in units of macroblocks of 16×16 pixels. At thedecoder side the compressed bit stream is taken and the original frame is restored. Emphasis isput on the implementation of CODEC at RTL level and investigate the effect of certain parameterssuch as Quantisation Parameter (QP) on overall compression of the frame rather than investigatingmultiple solutions of a specified block of CODEC.

H.264/AVC is the state-of-the-art video coding standard which promises to achieve same video quality at about half the bit rate of previous standards (H.263, MPEG-2). This tremendous achievement in compression and perceptual quality is due to the inclusion of various innovative tools. These tools are highly complex and data intensive as a result poses very heavy computational burden on the processors. De-blocking filter is one among them, it is the most time consuming part of the H.264/AVC reference decoder. In this thesis, a performance analysis of the de-blocking filter is made on Intel Pentium 4 processor and accordingly various optimization techniques have been studied and implemented. For some techniques statistical analysis of video data is done and according to the results obtained optimization is performed and for other techniques SIMD instructions has been used to achieve the optimization. Comparison of optimized techniques using SIMD with the reference software has shown significant speedup thus contributing to the real time implementation of the de-blocking filter on general purpose platform. / De-blocking Filter is the most time consuming part of the H.264 High Profile decoder. The process of De-block filtering specified in the H.264/AVC standard is sequential thus not computationally optimal. In this thesis various optimization algorithms have been studied and implemented. When compared to JM13.2 boundary strength algorithm, Static and ICME algorithms are quite primitive as a result no performance gain is achieved, in fact there is a decrease in performance. This dismal performance is due to various reasons, prominent among them are increased memory access, unrolling of loop to 4x4 boundary and early detection of intra blocks. When it comes to the optimization algorithms of Edge filtering module both the algorithms (SIMD and fast algorithm) showed significant improvement in performance when compared to JM13.2 edge filtering algorithm. This improvement is mainly due to the parallel filtering operation done in edge filtering module. Therefore, by using SSE2 instructions large speed up could be achieved on general purpose processors like Intel, while keeping the conformance with the standard.