In the last years, with more and more transistors can fit into a chip, the growth the IC design complexity is fast and original design flow can¡¦t cater for designers. Therefore, so many people promote to integrate the system into a single chip gradually with the last technology using the concept of hardware/software co-design. In this thesis, we use the hardware/software co-design concept to build a simple video codec from system level and implement it on the ARM¡¦s SOC platform. We focus on the hardware/software co-ordination. Because we use the platform-based design method, the build hardware/software modules can be used in the similar architecture on the ARM platform In our Video codec system, discrete wavelet transform(DWT) and RGBtoYCbCr are the most timing-consuming parts. Since DWT has inherent scalability and excellent features of energy compaction, it has been applied widely in the various image compression systems. We adopt the 5-3 filter lifting-based DWT in the hardware part of our system and design three different lifting-based DWT architectures by using the high level synthesis concept to optimize the hardware utilization and speed. In the premise of not increasing memory access times and additional processes of software, we overcome the boundary extension of DWT and verify it by means of FPGA after combining it with the RGBtoYCbCr hardware architecture. Finally, the hardware part is integrated with the other part implemented by software, we build a completely video encode system on the ARM SOC platform using the hardware/software co-design.

MP3 compression format is essential categorized one of the MPEG (Moving Picture Experts Group) standards for digital audio compression nowadays. For its superiority and convenient,MP3 has been widely used in multimedia player and storage application. In this thesis, we use software/hardware co-design methodology to design the MP3 player system. In addition, system level scheduling is adopted to arrange the execute time of SW and HW and significantly reduce the hardware cost under the construct of real-time processing. We can obtain fewer extra hardware cost while attaining the goal of real- time playing system. In order to perform software/hardware partitioning, simulate and analyze the MP3 application program to find out the critical parts with high time complexity and regular computation. These parts with high time complexity, e.g. IMDCT and Poly Phase synthesis filter bank, then are implemented by hardware to achieve better system performance. We use high level synthesis concept to optimize the hardware part and integrate software and hardware¡Asuch that communication between software and hardware can be performed smoothly. Finally, MP3 player system is using verified by hardware¡Bsoftware co- verified methodology on an SoC development platform. In order to build a complete verification environment, we attach extra input and output interfaces to the SoC development platform, e.g. the network card and sound card. Write some driver to drive related peripheral device. Since OS is conducive to the operations between software and hardware, Linux OS is ported to the SoC platform to manage software and hardware resources and drive the peripheral devices.

<p> </p><p>Modern nuclear and particle physics experiments run at a very high reaction rate and are able to deliver a data rate of up to hundred GBytes/s.  This data rate is far beyond the storage and on-line analysis capability. Fortunately physicists have only interest in a very small proportion among the huge amounts of data. Therefore in order to select the interesting data and reject the background by sophisticated pattern recognition processing, it is essential to realize an efficient data acquisition and trigger system which results in a reduced data rate by several orders of magnitude. Motivated by the requirements from multiple experiment applications, we are developing a high-end reconfigurable computation platform for data acquisition and triggering. The system consists of a scalable number of compute nodes, which are fully interconnected by high-speed communication channels. Each compute node features 5 Xilinx Virtex-4 FX60 FPGAs and up to 10 GBytesDDR2 memory. A hardware/software co-design approach is proposed to develop custom applications on the platform, partitioning performance-critical calculation to the FPGA hardware fabric while leaving flexible and slow controls to the embedded CPU plus the operating system. The system is expected to be high-performance and general-purpose for various applications especially in the physics experiment domain.</p><p>As a case study, the particle track reconstruction algorithm for HADES has been developed and implemented on the computation platform in the format of processing engines. The Tracking Processing Unit (TPU) recognizes peak bins on the projection plane and reconstructs particle tracks in realtime. Implementation results demonstrate its acceptable resource utilization and the feasibility to implement the module together with the sys-tem design on the FPGA. Experimental results show that the online track reconstruction computation achieves 10.8 - 24.3 times performance acceleration per TPU module when compared to the software solution on a Xeon2.4 GHz commodity server.</p>

Modern nuclear and particle physics experiments run at a very high reaction rate and are able to deliver a data rate of up to hundred GBytes/s.  This data rate is far beyond the storage and on-line analysis capability. Fortunately physicists have only interest in a very small proportion among the huge amounts of data. Therefore in order to select the interesting data and reject the background by sophisticated pattern recognition processing, it is essential to realize an efficient data acquisition and trigger system which results in a reduced data rate by several orders of magnitude. Motivated by the requirements from multiple experiment applications, we are developing a high-end reconfigurable computation platform for data acquisition and triggering. The system consists of a scalable number of compute nodes, which are fully interconnected by high-speed communication channels. Each compute node features 5 Xilinx Virtex-4 FX60 FPGAs and up to 10 GBytesDDR2 memory. A hardware/software co-design approach is proposed to develop custom applications on the platform, partitioning performance-critical calculation to the FPGA hardware fabric while leaving flexible and slow controls to the embedded CPU plus the operating system. The system is expected to be high-performance and general-purpose for various applications especially in the physics experiment domain. As a case study, the particle track reconstruction algorithm for HADES has been developed and implemented on the computation platform in the format of processing engines. The Tracking Processing Unit (TPU) recognizes peak bins on the projection plane and reconstructs particle tracks in realtime. Implementation results demonstrate its acceptable resource utilization and the feasibility to implement the module together with the sys-tem design on the FPGA. Experimental results show that the online track reconstruction computation achieves 10.8 - 24.3 times performance acceleration per TPU module when compared to the software solution on a Xeon2.4 GHz commodity server. / QC 20101118

Application specific instruction set processors become part of every day life although it's not always visible at first sight. During their development it's needed to somehow describe their architecture, instruction set and behavior. To make their developement worth, it's necessary to be able to create applications for these processors and during application development errors are always made. Debuggers serve to discover and help fixing them. This paper summarises some basic information to debugger development and describes implementation for processors created using the Lissom project.

La estimación y verificación de las prestaciones de los diseños de sistemas embebidos de la forma más rápida posible al principio del proceso de diseño es un hito de gran importancia. Por ello, esta tesis propone una nueva solución basada en simulación por anotación de código fuente, que a costa de algo de precisión, permite realizar simulaciones muy rápidas con un mínimo esfuerzo de diseño. La primera tarea realizada en esta tesis ha sido extender el lenguaje SystemC para incluir primitivas de un sistema operativo de tiempo real(RTOS) que permiten la ejecución y el refinado de módulos software. La segunda parte de la tesis se ha centrado en la generación de una librería capaz de obtener datos dinámicamente sobre las prestaciones temporales de dichos sistemas a partir del código fuente, para poder verificar el cumplimiento de las características requeridas. Junto con los elementos SW se han desarrollado componentes SystemC de alto nivel capaces de modelar los elementos principales de un sistema embebido, como buses, memorias, redes de comunicaciones, etc. Por último se han desarrollado los componentes necesarios para poder incluir toda esta infraestructura en procesos de exploración automática del proceso de diseño, de forma que en base a descripciones iniciales del sistema en formato XML. La infraestructura de simulación y estimación de rendimiento ha sido desarrollada y probada en diversos proyectos europeos. / Estimating and verifying system performance of embedded designs at the beginning of the design process is a very important task. Fast estimation tools are required in order to evaluate different design possibilities, such as HW/SW partitioning or resource allocation, to verify the fulfillment of the system constraints, or to support design space exploration flows. In this context, the thesis proposes a tool capable of simulating embedded systems using source code annotation. As a consequence, fast estimations are obtained with minimal design effort, obtaining an adequate accuracy. For developing such tool several tasks has been performed. First, the SystemC language has been extended to provide the designer with a model of a real-time operating system. This model enables the correct simulation, scheduling and debugging of embedded SW. The second element added is an infrastructure capable of estimating and annotating performance information for each basic block in the source code. This infrastructure enables obtaining timed simulations of the SW. Additionally generic TLM elements have been developed to enable creating models of the HW platforms. Finally, additional components has been developed to use the proposed tool in a complete Design Space Exploration flow. The simulation infrastructure has been developed and checked in several European projects, and in collaboration with private companies.

<p>This thesis proposes SoPC (System on a Programmable<br />Chip) architectures for efficient embedding of vison-based<br />localization and obstacle detection tasks in a navigational<br />pipeline on autonomous mobile robots. The obtained<br />results are equivalent or better in comparison to state-ofthe-<br />art. For localization, an efficient hardware architecture<br />that supports EKF-SLAM&#39;s local map management with<br />seven-dimensional landmarks in real time is developed.<br />For obstacle detection a novel method of object<br />recognition is proposed - detection by identification<br />framework based on single detection window scale. This<br />framework allows adequate algorithmic precision and<br />execution speeds on embedded hardware platforms.</p> / <p>Ova teza bavi se dizajnom SoPC (engl. System on a<br />Programmable Chip) arhitektura i algoritama za efikasnu<br />implementaciju zadataka lokalizacije i detekcije prepreka<br />baziranih na viziji u kontekstu autonomne robotske<br />navigacije. Za lokalizaciju, razvijena je efikasna<br />računarska arhitektura za EKF-SLAM algoritam, koja<br />podržava skladi&scaron;tenje i obradu sedmodimenzionalnih<br />orijentira lokalne mape u realnom vremenu. Za detekciju<br />prepreka je predložena nova metoda prepoznavanja<br />objekata u slici putem prozora detekcije fiksne<br />dimenzije, koja omogućava veću brzinu izvr&scaron;avanja<br />algoritma detekcije na namenskim računarskim<br />platformama.</p>

Un véhicule autonome ou un robot mobile est équipé d'un système de navigation qui doit comporter plusieurs briques fonctionnelles pour traiter de perception, localisation, planification de trajectoires et locomotion. Dès que ce robot ou ce véhicule se déplace dans un environnement humain dense, il exécute en boucle et en temps réel plusieurs fonctions pour envoyer des consignes aux moteurs, pour calculer sa position vis-à-vis d'un repère de référence connu, et pour détecter de potentiels obstacles sur sa trajectoire; du fait de la richesse sémantique des images et du faible coût des caméras, ces fonctions exploitent souvent la vision. Les systèmes embarqués sur ces machines doivent alors intégrer des cartes assez puissantes pour traiter des données visuelles en temps réel. Par ailleurs, les contraintes d'autonomie de ces plateformes imposent de très faibles consommations énergétiques. Cette thèse proposent des architectures de type SOPC (System on Programmable Chip) conçues par une méthodologie de co-design matériel/logiciel pour exécuter de manière efficace les fonctions de localisation et de détection des obstacles à partir de la vision. Les résultats obtenus sont équivalents ou meilleurs que l'état de l'art, concernant la gestion de la carte locale d'amers pour l'odométrie-visuelle par une approche EKF-SLAM, et le rapport vitesse d'exécution sur précision pour ce qui est de la détection d'obstacles par identification dans les images d'objets (piétons, voitures...) sur la base de modèles appris au préalable. / An autonomous mobile platform is endowed with a navigational system which must contain multiple functional bricks: perception, localization, path planning and motion control. As soon as such a robot or vehicle moves in a crowded environment, it continously loops several tasks in real time: sending reference values to motors' actuators, calculating its position in respect to a known reference frame and detection of potential obstacles on its path. Thanks to semantic richness provided by images and to low cost of visual sensors, these tasks often exploit visual cues. Other embedded systems running on these mobile platforms thus demand for an additional integration of high-speed embeddable processing systems capable of treating abundant visual sensorial input in real-time. Moreover, constraints influencing the autonomy of the mobile platform impose low power consumption. This thesis proposes SOPC (System on a Programmable Chip) architectures for efficient embedding of vison-based localization and obstacle detection tasks in a navigational pipeline by making use of the software/hardware co-design methodology. The obtained results are equivalent or better in comparison to state-of-the-art for both EKF-SLAM based visual odometry: regarding the local map size management containing seven-dimensional landmarks and model-based detection-by-identification obstacle detection: algorithmic precision over execution speed metric.