Global ETD Search

1	Hardware design based on Verilog HDL Pace, Gordon G. January 1998 (has links) No description available. 005 Hardware description languages
2	Integration of VHDL simulation and test verification into a Process Model Graph design environment / Dailey, David M., January 1994 (has links) Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 116-117). Also available via the Internet.
3	A framework for synthesis from VHDL / Shah, Sandeep R., January 1991 (has links) Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1991. / Vita. Abstract. Includes bibliographical references (leaves 91-94). Also available via the Internet.
4	Behavior modeling of RF systems with VHDL / Sama, Anil, January 1991 (has links) Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1991. / Vita. Abstract. Includes bibliographical references (leaf 107). Also available via the Internet.
5	Rapid development of VHDL behavioral models / Wright, Philip A., January 1992 (has links) Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1992. / Vita. Abstract. Includes bibliographical references (leaves 56-57). Also available via the Internet.
6	A hierarchical approach to effective test generation for VHDL behavioral models / Rao, Sanat R., January 1993 (has links) Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 147-149). Also available via the Internet.
7	The semantics of VHDL with VAL and HOL towards practical verification tools / Van Tassel, John P. January 1900 (has links) Thesis (M.A.)--Wright State University, 1990. / Cover title. "June 1990." Includes bibliographical references.
8	Digital system synthesis with standard EDIF output Blanton, Ronald DeShawn, 1965- January 1989 (has links) In the growing field of digital system design, there is a great need for design tools that will assist the engineer in developing large scale systems. AHPL, A Hardware Programming Language, is a hardware description language which allows a digital system to be described, evaluated, and analyzed. But like many design tools, AHPL cannot satisfy the multitude of design tool applications. In order to enhance the power of AHPL as a design tool, an EDIF translator is developed. The EDIF translator generates an EDIF netlist of an AHPL design, thus making it possible to port AHPL designs to other design tools. Computer engineering. Computer hardware description languages.
9	Femto-VHDL : the semantics of a subset of VHDL and its embedding in the HOL proof assistant Van Tassel, John Peter January 1993 (has links) No description available. 005
10	RTL AND SWITCH-LEVEL SIMULATION COMPARISON ON EIGHT BIT MICROPROCESSOR Lai, Jiunn-Yiing, 1958- January 1987 (has links) In this research, an AHPL (A Hardware Programming Language) based automation system is used to design and verify the Intel-8080 microprocessor from the RTL (Register Transfer Level) hardware description through the network list of transistors. The HPSIM is used as a RTL simulator which interprets the AHPL description and executes the connections, branches, and register transfer, and prints line or register values for each circuit clock period. After the AHPL description has been translated to switch-level link list, ESIM is applied for more detailed simulation to ensure the digital behavior in this microprocessor design is correct. The ESIM is an event-driven switch-level simulator which accepts commands from the user, and executes each command before reading the next one. After performing these different levels of simulations, a comparison is discussed at the end. Computer hardware description languages. Computer simulation.

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