Global ETD Search

31	Suitability of the SRC-6E reconfigurable computing system for generating false radar image / Macklin, Kendrick R. January 2004 (has links) (PDF) Thesis (M.S. in Computer Science)--Naval Postgraduate School, June 2004. / Thesis advisor(s): Neil Rowe. Includes bibliographical references (p. 129-130). Also available online.
32	Benchmarking and analysis of the SRC-6E reconfigurable computing system / Macklin, Kendrick R. January 2003 (has links) (PDF) Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, December 2003. / Thesis advisor(s): Douglas Fouts, Ted Lewis. Includes bibliographical references (p. 125). Also available online.
33	UML modeling for VHDL designs / Unified Modeling Language modeling for Very High Speed Integrated Circuit Hardware Description Language designs Sprunger, Steven J. January 2008 (has links) Unified Modeling Language (UML) allows software engineers to use a standard way of expressing a design approach at a high level. The benefits of system modeling are well accepted in the software development community. Modeling of Very High Speed Integrated Circuit Hardware Description Language (VHDL) designs, for synthesizing into hardware, is a common practice also. The research herein looks at system modeling of a design using UML, in which there are both software and hardware components. The idea is to explore modeling of the system with the ability to abstract whether the implementation of a particular function is realized in software or hardware. The designer can then model/evaluate a given system design approach and later allocate functions to software and hardware, as appropriate to meet constraints such as performance, cost, schedule. Since using UML for software is a standard approach, this research investigates the UML to hardware path via VHDL. / Department of Computer Science UML (Computer science) Computer engineering.
34	A parametrized CAD tool for VHDL model development with X Windows / Singh, Balraj, January 1990 (has links) Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1990. / Vita. Abstract. Includes bibliographical references (leaves 52-54). Also available via the Internet.
35	Assertion-checker synthesis for hardware verification, in-circuit debugging and on-line monitoring Boulé, Marc. January 1900 (has links) Thesis (Ph.D.). / Written for the Dept. of Electrical and Computer Engineering. Title from title page of PDF (viewed 2008/05/09). Includes bibliographical references.
36	Optimization techniques for distributed Verilog simulation Li, Lijun, January 1900 (has links) Thesis (Ph.D.). / Written for the School of Computer Science. Title from title page of PDF (viewed 2008/02/12). Includes bibliographical references.
37	Aspects of hardware methodologies for the NTRU public-key cryptosystem / Wilhelm, Kyle. January 2008 (has links) Thesis (M.S.)--Rochester Institute of Technology, 2008. / Typescript. Includes bibliographical references (p. 69-72).
38	Hazard detection with VHDL in combinational logic circuits with fixed delays / Chu, Ming-Cheung, January 1992 (has links) Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1992. / Vita. Abstract. Includes bibliographical references (leaves 181-182). Also available via the Internet.
39	Representation and simulation of a high level language using VHDL / Edwards, Carleen Marie, January 1994 (has links) Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 56-57). Also available via the Internet.
40	VHDL modeling and design of an asynchronous version of the MIPS R3000 microprocessor / Fanelli, Paul. January 1994 (has links) Thesis (M.S.)--Rochester Institute of Technology, 1994. / Typescript. Includes bibliographical references (leaves 124-125).

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