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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
21

Hierarchical test generation for VHDL behavioral models /

Pan, Bi-Yu, January 1992 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1992. / Vita. Abstract. Includes bibliographical references (leaves 89-90). Also available via the Internet.
22

Mapping conceptual graphs to primitive VHDL processes /

Shrivastava, Vikram M., January 1994 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaf 66). Also available via the Internet.
23

Generation of VHDL from conceptual graphs of informal specifications /

Honcharik, Alexander J., January 1993 (has links)
Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaf 64). Also available via the Internet.
24

QoS-driven composition analysis for component-based system development /

Ma, Hui. January 2007 (has links)
Thesis (Ph. D.)--University of Texas at Dallas, 2007. / Includes vita. Includes bibliographical references (leaves 201-214)
25

Ephedra: a C to Java migration environment

Martin, Johannes 30 October 2018 (has links)
The Internet has grown in popularity in recent years, and thus it has gained importance for many current businesses. They need to offer their products and services through their Web sites. To present not only static content but also interactive services, the logic behind these services needs to be programmed. Various approaches for programming Web services exist. The Java programming language can be used to implement Web services that run both on Internet clients and servers, either exclusively or in interaction with each other. The Java programming language is standardised across computing platforms and has matured over the past few years, and is therefore a popular choice for the implementation of Web services. The amount of available and well-tested Java source code is still small compared to other programming languages. Rather than taking the risks and costs of redeveloping program libraries, it is often preferable to move the core logic of existing solutions to Java and then integrate it into Java programs that present the services in a Web interface. In this Ph.D. dissertation, we survey and evaluate a selection of current approaches to the migration of source code to Java. To narrow the scope of the dissertation to a reasonable limit, we focus on the C and C++ programming languages as the source languages. Many mature programs and program libraries exist in these languages. The survey of current migration approaches reveals a number of their restrictions and disadvantages in the context of moving program libraries to Java and integrating them with Java programs. Using the experiences from this survey, we established a number of goals for an improved migration approach and developed the Ephedra approach by closely following these goals. To show the practicality of this approach, we implemented an automated tool that performs the migration according to the Ephedra approach and evaluated the migration process and its result with respect to the goals we established using selected case studies. Ephedra provides a high degree of automation for the migration process while letting the software-engineer make decisions where multiple choices are possible. A central problem in the migration from C to Java is the trans formation of C pointers to Java references. Ephedra provides two different strategies for this transformation and explains their applicability to subject systems. The code resulting from a migration with Ephedra is maintainable and functionally equivalent to the original code save some well documented exceptions. Performance trade-offs are analysed and evaluated in the light of the intended subject systems. / Graduate
26

A methodology for analyzing hardware description language specifications of legacy designs

Costi, Claudio 07 June 2018 (has links)
In order to increase productivity, methodologies based on reuse of previously designed components are exploited by the Integrated Circuit (IC) design community. However, designers are often faced with the problem of reusing a legacy design for which the behavior is unclear due to missing documentation and the complexity of the design. In this dissertation a methodology to assist designers in retrieving the original intent of a design from its Hardware Description Language (HDL) specification is described. The methodology is based on code analysis and techniques which produce different views of HDL code. These views represent the behavior of a design in more abstract terms than the HDL code. / Graduate
27

Design, implementation, and testing of a software interface between the AN/SPS-65(V)1 radar and the SRC-6E reconfigurable computer /

Guthrie, Thomas G. January 2005 (has links) (PDF)
Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, March 2005. / Thesis Advisor(s): Douglas J. Fouts. Includes bibliographical references (p. 61). Also available online.
28

ADH, Aspect Described Hardware-Description-Language : a thesis submitted in partial fulfilment of the requirements for the degree of Master of Engineering in Electrical and Electronic Engineering in the University of Canterbury /

Park, Su-Hyun. January 1900 (has links)
Thesis (M.E.)--University of Canterbury, 2006. / Typescript (photocopy). "March 2006." Includes bibliographical references (p. 145-151). Also available via the World Wide Web.
29

Suitability of the SRC-6E reconfigurable computing system for generating false radar image

Macklin, Kendrick R. 06 1900 (has links)
Approved for public release; distribution is unlimited / Communication is an essential skill for every military officer. Their jobs are accomplished through communication This thesis evaluates the usefulness of the SRC-6E reconfigurable computing system for a radar signal processing application and documents the process of creating and importing VHDL code to configure the user definable logic on the SRC-6E. The research builds on previous work which implemented a false radar imaging algorithm on the SRC-6E. Data from alternative computational approaches to the same problem are compared to determine the effectiveness of SRC-6E solution. The results show that the SRC-6E provides and effective solution for implementations with greater than 64 range bins. An evaluation of the SRC-6E difficulty of use is conducted, including a discussion of required skills, experience and development times. The algorithm test code is included in the appendices.
30

Spécifications systèmes et synthèses de la communication pour le co-design logiciel/matériel

DAVEAU, Jean Marc 19 December 1997 (has links) (PDF)
Au fur et à mesure que la complexité s'accroit, il devient nécessaire de définir de nouvelles méthodes permettant de la gérer. Une des façons de maîtriser cette complexité est d'élever le niveau d'abstraction des spécifications en utilisant des langages de spécification systèmes. D'un autre côté, l'élévation du niveau d'abstraction augmente le fossé entre les concepts utilisés pour la spécification (processus communicants, communication abstraite) et ceux utilisés par les langages de description de matériel. Bien que ces langages soient bien adaptés à la spécification et la validation de systèmes complexes, les concepts qu'ils manipulent ne sont pas aisément transposables sur ceux des langages de description de matériels. Il est donc nécessaire de définir de nouvelles méthodes permettant une synthèse efficace à partir de spécifications systèmes. Le sujet de cette thèse est la présentation d'une approche de génération de code C et VHDL à partir de spécifications systèmes en SDL. Cette approche résout la principale difficulté rencontrée par les autres approches, à savoir la communication inter-processus. La communication SDL peut être traduite en VHDL en vue de la synthèse. Cela est rendu possible par l'utilisation d'une forme intermédiaire qui supporte un modèle de communication générale qui autorise la représentation pour la synthèse de la plupart des schémas de communication. Cette forme intermédiaire permet d'appliquer au système un ensemble d'étapes de raffinement pour obtenir la solution désirée. La principale étape de raffinement, appelée synthèse de la communication, détermine le protocole et les interfaces utilisés par les différents processus pour communiquer. la spécification raffinée peut être traduite en C et VHDL pour être utilisée par des outils du commerce. Nous illustrons la faisabilité de cette approche par une application à un système de télécommunication : le protocole TCP/IP sur ATM.

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