The use of Computer Hardware Description Languages plays an important role in the design automation process of digital systems. These languages help hardware engineers to provide a precise description of the internal structure of a system, and one of the most significant uses of these languages is as a means of input to a system simulator. AHPL is a hardware description language that describes a digital system as a set of modules and units. This language is supported by a function-level simulator (HPSIM2), but the simulator only provides support to the module descriptions of a system. This paper presents an improved version of the simulator that supports the use of unit descriptions called Combinational Logic Units or CLUNITs. The syntax and structure of a CLUNIT is analyzed, the operation and data structure of the simulator is given; and several examples are given to support these discussions.

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Thesis (M.Eng.)--Memorial University of Newfoundland, 2001. / Restricted until June 2002. Bibliography: leaves 96-98.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, June 2003. / Thesis advisor(s): Douglas J. Fouts, Phillip E. Pace. Includes bibliographical references (p. 143-144). Also available online.

An essential requirement for the design of large VLSI circuits is a design methodology which would allow the designer to overcome the complexity and correctness issues associated with the building of such circuits. We propose that many of the problems of the design of large circuits can be solved by using a formal design notation based upon the functional programming paradigm, that embodies design concepts that have been used extensively as the framework for software construction. The design notation should permit parallel, sequential, and recursive decompositions of a design into smaller components, and it should allow large circuits to be constructed from simpler circuits that can be embedded in a design in a modular fashion. Consistency checking should be provided as early as possible in a design. Such a methodology would structure the design of a circuit in much the same way that procedures, classes, and control structures may be used to structure large software systems. However, such a design notation must be supported by tools which automatically check the consistency of the design, if the methodology is to be practical. In principle, the methodology should impose constraints upon circuit design to reduce errors and provide' correctness by construction' . It should be possible to generate efficient and correct circuits, by providing a route to a large variety of design tools commonly found in design systems: simulators, automatic placement and routing tools, module generators, schematic capture tools, and formal verification and synthesis tools.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1990. / Vita. Abstract. Includes bibliographical references (leaves 74-75). Also available via the Internet.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 95-98). Also available via the Internet.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 126-128). Also available via the Internet.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 99-101). Also available via the Internet.