Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 165-169). Also available via the Internet.

Thesis (Ph. D.)--Oregon Graduate Institute, 2000.

Thesis (M.S.)--Rochester Institute of Technology, 1995. / Typescript. Bibliography: leaf 55.

Thesis (M.S.)--Virginia Polytechnic Institute and State University, 1993. / Vita. Abstract. Includes bibliographical references (leaves 79-80). Also available via the Internet.

Report (M.S.)--Virginia Polytechnic Institute and State University, 1994. / Vita. Abstract. Includes bibliographical references (leaves 60-62). Also available via the Internet.

We present the first dynamic algorithm that maintains a clique tree representation of a chordal graph and supports the following operations: (1) query whether deleting or inserting an arbitrary edge preserves chordality, (2) delete or insert an arbitrary edge, provided it preserves chordality. We give two implementations. In the first, each operation runs in O( n) time, where n is the number of vertices. In the second, an insertion query runs in O(log² n) time, an insertion in O(n) time, a deletion query in O(n) time, and a deletion in O(n log n) time. We also introduce the clique-separator graph representation of a chordal graph, which provides significantly more information about the graph's structure than the well-known clique tree representation. We present fundamental properties of the clique-separator graph and additional properties when the input graph is interval. We then introduce the train tree representation of interval graphs and use it to decide whether there is a certain linear ordering of the graph's maximal cliques. This yields a fully dynamic algorithm to recognize interval graphs in O(n log n) time per edge insertion or deletion. The clique-separator graph may lead to dynamic algorithms for every proper subclass of chordal graphs, and the train tree may lead to fast dynamic algorithms for problems on interval graphs. / Graduate

Made available in DSpace on 2015-04-22T22:00:45Z (GMT). No. of bitstreams: 1 Hillermann Ferreira Osmidio Lima.pdf: 1820292 bytes, checksum: 0434ed2f2545deea32acce6f4ff7b7c3 (MD5) Previous issue date: 2012-12-18 / This dissertation presents an implementation in VHDL of the MTP-2 layer of SS7, Low part, together with a Programmable Switching Matrix, to reach, as more generic as possible, a modular, portable (reusable) and scalable solution to be used in various technologies and telecommunications equipments with different architectures and capabilities. As parallel contributions, this work includes: the development of a methodology for implementing digital circuits in VHDL based on a visual description using flowcharts; the proposing of a technique for generating random vectors using the MATLAB software for simulation and validation of digital circuits using hardware description language, allowing the detection of fault conditions that would hardly be evaluated with manually generated vectors. As a result, this work generated practical use artifact, presenting a substantial increase capacity on treatment of SS7 links in telecommunications equipments, when compared with previous related works. / Esta dissertação apresenta uma implementação em VHDL da camada MTP-2 da SS7, parte Low, em conjunto com uma Matriz de Comutação Programável de modo a constituir, da forma mais genérica possível, uma solução modular, portável (reutilizável) e escalável para poder ser usada em várias tecnologias e em equipamentos de telecomunicações com diferentes arquiteturas e capacidades. Como contribuições paralelas do trabalho destacam-se: o desenvolvimento de uma metodologia para implementação em VHDL de circuitos digitais a partir de uma descrição visual com o uso de fluxogramas; a proposta de uma técnica de geração de vetores de forma aleatória usando o software MATLAB para simulação e validação de circuitos digitais usando linguagem de descrição de hardware, permitindo a detecção de condições de falha que dificilmente seriam avaliadas com vetores gerados de forma manual. Como resultado, este trabalho gerou artefato de utilização prática, apresentando um considerável aumento na capacidade de tratamento de Enlaces SS7 de equipamentos de telecomunicações, quando comparado com trabalhos realizados anteriormente.

Lab-on-a-Chip systems and the associated micro-fabrication technologies have been around for almost three decades. However, the rapidly shifting technological landscape and the multidisciplinary nature of the engineering know-how have made it extremely difficult for a majority of these technologies to materialize to find applications and find commercial products. In order to address this gap, researchers worldwide have attempted to implement design automation paradigms typically used for VLSI engineering and apply them to these Lab-on-a-Chip. However, almost all of these efforts have been disconnected, resulting in a delayed/stalled application of algorithmic advances on real-world device design. FluigiCAD will allow the rapid application and integration of innovative ideas into a single cohesive workflow. / 2024-06-13T00:00:00Z

This thesis describes the design and implementation of a hardware synthesis system based on design descriptions provided in VHDL. Several aspects of the synthesis problem are examined. These include the design of an internal format to represent multiple levels of design information, algorithms for synthesis, optimizations, and verification of the synthesis process. Key features of this system include the ability to synthesize models that span a wide range of design description abstraction levels. The synthesis system internal format contains data structures for algorithmic, dataflow, as well as structural VHDL constructs. This framework for performing synthesis over a wide range of abstraction levels is the novel feature of this system. Optimizations for register-transfer level (dataflow) models are discussed along with their implementation. The design and implementation of the synthesis library, which contains information about the hardware components available to perform the synthesis, is also discussed. The output of the synthesis system is in the form of two files, an RNL format netlist and a purely structural VHDL netlist. In order to produce the actual hardware layout, the RNL netlist must be input to VPNR, a standard cell place and route system. The structural VHDL may be simulated to verify the synthesis process. Results of mixed level synthesis are provided. / Master of Science

This thesis describes the development of the Hierarchical Behavioral Test Generator (HBTG) for the testing of VHDL behavioral models. HBTG uses the Process Model Graph of the VHDL behavioral model as the base for test generation. Test sets for individual processes of the model are precomputed and stored in the design library. Using this information, HBTG hierarchically constructs a test sequence that tests the functionality of the model. The test sequence generated by HBTG is used for the simulation of the model. Various features present in HBTG and the implementation of the algorithm are discussed. The idea of an effective test sequence for a VHDL behavioral model is proposed. A system is presented to evaluate the quality of the test sequence generated by the algorithm. Test sequences and coverage results are given for several models. Some suggestions for future improvements to the tools are made. The HBTG forms part of a complete CAD system for rapid development and testing of VHDL behavioral models. / Master of Science