Recent advances in wireless communication industry, radio- frequency circuits are developing fast. For power amplifiers, the active circuits are mainly composed of transistors where withstand high voltage and current. The excellent transistors characteristic result in good circuit performances. In the thesis, the modeling of InGaAs pseudomorphic high electron mobility transistor was provided by Win Semiconductor Corporation. The established small signal model contains extrinsic and intrinsic elements. The extrinsic elements are extracted by simple method without fitting process for long time. Then, the intrinsic elements are obtained by conventional matrix transformations. The each element of models is varied with different gate width area are also discussed. Finally, the nonlinear models are expanded upon the concept of small signal model. Due to some of intrinsic elements are significantly varied with bias, small signal models have not applied to nonlinear circuit simulations. For developing nonlinear models, the nonlinear elements characteristics are described by empirical fitting equations. The accuracy of models is achieved by comparing simulated and on wafer measurement results, including DC¡Bsmall signal and large signal power characteristics.

Cette thèse est une contribution à l'étude de composés semiconducteurs InX Al1-X N à forte teneur en Indium. Ces composés présentent des propriétés très intéressantes pour des applications dans le domaine de l'amplification des hyperfréquences. L'objectif principal de la thèse est de définir des hétéro-structures de type AlGaInN / GaN, pour transistors à Effet de Champ Piézoélectrique (HEMT), épitaxiées sur substrats de saphir, silicium, et SiC, optimisées en vue de l'amplification hyperfréquence. Dans la première partie, nous étudions la croissance épitaxiale de couches minces du composé binaire GaN, en phase vapeur, à partir de précurseurs organométalliques (MOVPE), dans des conditions optimisées pour obtenir des couches fortement résistives. La deuxième partie est consacrée à l'étude de structures HEMT AlGaN/GaN sur SiC et sur silicium. Sur SiC, nous montrons la forte influence des propriétés du substrat sur les propriétés électriques des structures HEMT. Nous avons étudié une structure nouvelle incluant une fine couche de AlN entre les couches AlGaN et GaN et évalué les performances de transistors HEMT AlGaN/GaN et AlGaN/AlN/GaN sur SiC et sur Silicium (111). La partie suivante est consacrée à la croissance de composés ternaires InAlN. Nous avons étudié l'influence de la température de croissance et du rapport V/III sur les propriétés structurales de InAlN. Les conditions optimales ont été utilisées pour la réalisation de structures HEMT InAlN/AlN/GaN. Nous démontrons l'influence considérable de la couche AlN sur les propriétés électriques de ces structures. Enfin, nous discutons les performances obtenues sur des transistors à effet de champ InAlN/AlN/GaN sur SiC / This work reports on the metal-organic vapor phase epitaxy and on the characterisation of III-N GaInAlN heterostructures for High Electron Mobility Transistors. In a first part, the heteroepitaxy of semiinsulating GaN layers on sapphire, SiC and silicon is presented as the basis for the subsequent growth of III-N HEMT structures. The influence of suitable nucleation layers on the properties of GaN is presented and discussed. A second part deals with AlGaN/GaN HEMT structures grown on SiC and on Si (111) wafers. The influence of SiC substrate properties on the electrical performances of AlGaN/GaN HEMT is presented. A novel structure, including a thin AlN interlayer between the GaN buffer layer and the AlGaN barrier layer has also been introduced. The section is completed by device results obtained on selected heterostructures. A study of the impact of selected growth parameter (i.e. growth temperature, V/III ratio) on the structural and surface properties of InAlN layers is then presented. The optimized conditions have been used for the growth InAlN/AlN/GaN HEMT structures which have been thoroughly characterized. The electrical properties of the structures were found to be strongly dependent on the growth conditions of the AlN interlayer (e.g. deposition time, V/III ratio). Finally, state of the art device results obtained with InAlN/AlN/GaN heterostructures are presented

Les travaux présentés dans ce manuscrit sont axés sur le développement et la caractérisation de modules technologiques sur semiconducteurs à large bande interdite à base de nitrure de gallium (GaN), pour la réalisation de transistors et de cathodes froides. Ils ont été réalisés au sein du laboratoire III-V lab, commun aux entités : Alcatel - Thales - CEA Leti. Notre projet de recherche a bénéficié d'un soutien financier assuré par Thales Electron Devices (TED) et l'Agence Nationale de la Recherche ( ANR ). Concernant les transistors HEMT III-N, nos investigations se sont focalisées sur le développement des parties actives des transistors, incluant principalement la structuration des électrodes de grilles, l'étude de la passivation des grilles métalliques, ainsi que l'étude de diélectriques de grille pour la réalisation de structures MIS-HEMT.Les transistors MOS-HEMT « Normally-off » réalisés présentent des performances comparables à l'état de l'art, avec une densité de courant de drain maximum comprise entre 270 mA et 400 mA / mm, un ratio ION / IOFF > 1100, et des tensions de claquage > 200V. Les tensions de seuil sont comprises entre + 1,8 V et + 4 V. Nos contributions au développement des cathodes froides ont permis de démontrer une première émission dans le vide à partir de cathodes GaN, avec une densité de courant maximale de 300 µA / cm2 pour une tension de polarisation de 40 V / The results presented in this manuscript relate to technological developments and device processing on wide bandgap III-N semiconductor materials. They have been focused on III-N HEMT transistors and GaN cold cathodes. They have been realised within the III-V lab, which is a common entity between: Alcatel - Thales - CEA Leti. They have been financially supported by Thales Electron Devices company (TED) and the French National Research Agency ( ANR ). Regarding III-N HEMTs, our investigations have been focused on the development of device gate processing, which includes : the structuration of gate electrodes, the study of device passivation, and the realization of Metal-Insulator-Semiconductor High Mobility Electron Transistors ( MIS-HEMTs ). The “ Normally-off ” MOS-HEMT structures we have realized exhibit performances comparable to the state of the art, with a maximum drain current density between 270 and 400 mA / mm, a ION / IOFF ratio > 1.100, and a breakdown voltage > 200V. The threshold voltage values range between + 1,8 V and + 4V. We have also been able to demonstrate prototype GaN cold cathodes providing a maximum current density of 300 µA / cm2, emitted in vacuum for a bias voltage around 40 V

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) are promising candidates for next generation high-efficiency and high-voltage power applications. The excellent physical properties of GaN-based materials, featuring high critical electric field and large carrier saturation velocity, combined to the high carrier density and large mobility of the two-dimensional electron gas confined at the AlGaN/GaN interface, enable higher power density minimizing power losses and self-heating of the device. However, the advent of the GaN-based MIS-HEMT to the industrial production is still hindered by technological challenges that are being faced in parallel. Among them, one of the biggest challenge is represented by the insertion of a gate dielectric in MIS-HEMTs compared to Schottky-gate HEMTs, which causes operational instability due to the presence of high-density trap states located at the dielectric/III-nitride interface or within the dielectric. The development of a gold-free ohmic contact technology is another important concern since the high-volume and cost-effective production of GaN-based transistors also depends on the cooperative manufacturing of GaN-based devices in Si production facilities, where gold represents an undesidered source of contamination. In fact, even though over the past years there have been multiple attemps to develop gold-free ohmic contacts, there is still no full understanding of the contact formation and current transport mechanism. The first objective of this work was the investigation of a gold-free and low-resistive ohmic contact technology to AlGaN/GaN based on sputtered Ta/Al-based metal stacks annealed at low temperatures. A low contact resistance below 1 Ω mm was obtained using Ta/Al-based metal stacks annealed at temperatures below 600 °C. The ohmic behavior and the contact properties of contact resistance, optimum annealing temperature and thermal stability of Ta/Al-based contacts were studied. The nature of the current transport was also investigated indicating a contact mechanism governed by thermionic field emission tunneling through the AlGaN barrier. Finally, gold-free Ta/Al-based ohmic contacts were integrated in MIS-HEMTs fabricated on a 150 mm GaN-on- Si substrate, demonstrating to be a promising contact technology for AlGaN/GaN devices and revealing to be beneficial for devices operating at high temperatures. The optimization of the MIS-gate structure in terms of trap states at the dielectric/III-nitride interface and inside the dielectric in MIS-HEMTs using atomic layer deposited (ALD) Al2O3 as gate insulator was the second focus of this work. First, the MIS-gate structure was improved by an O2 plasma surface preconditioning applied before the Al2O3 deposition and by an N2 postmetallization anneal applied after gate metallization, which significantly reduced trap states at the Al2O3/GaN interface and within the dielectric. Afterwards, the effectiveness of these treatments was demonstrated in Al2O3-AlGaN/GaN MIS-HEMTs by pulsed current–voltage measurements revealing improved threshold voltage stability. Lastly, it was shown that also the lower annealing temperatures used for the formation of Ta/Al-based ohmic contacts, processed before gate dielectric deposition, are beneficial in terms of trap states at the ALD-Al2O3/GaN interface, representing a new aspect to be considered when using an ohmic first fabrication approach.

Gallium Nitride (GaN) and its alloys with InN and AlN, the III-nitrides, are of interest for a variety of high power-high frequency electronics and optoelectronics applications. However, unlike Si and GaAs technology that have been developed on native substrates, III-nitride devices have been developed on non-native substrates such as Si, sapphire and SiC. This is because bulk cheap native III-nitride substrates are unavailable. Among the known substrates, III-nitride technology development on Si is desirable because of its large substrate size and low cost. However, the large lattice and thermal expansion mismatch between the III-nitrides films and Si substrate leads to a high level of dislocations, 1010 cm-2, and tensile stress which results in cracking. For successful integration of crack free and low dislocation density GaN on Si various kinds of transition layer schemes are used that help to incorporate a compressive growth stress to neutralize the tensile thermal mismatch stresses and also to reduce dislocation densities to levels required by devices. These transition schemes, ranging from 400 nm to 7 m, involve the use of graded AlGaN layers, high/low temperature interlayers and superlattices. The aim of the research described in this thesis was a systematic comparison of the different transition layer schemes currently used with the objective of increasing the efficiency of integrating device quality, crack free, low dislocation density, <109 cm-2, GaN with Si. A metal organic chemical vapor deposition equipped with an in-situ stress monitor was used for growth. Transmission electron microscopy was used for quantitative measurement of dislocation density. The research shows, for the first time, that all transition layer optimization depends critically on the Si surface made available for growth of the first AlN layer. It needs to be optimally cleaned such that it is oxide free and smooth. A quantitative TEM comparison of various currently used transition layer schemes shows that while they have interesting mechanistic differences, they are not very different in their dislocation reduction efficiency. All of them yield a final dislocation density in a probe GaN layer of 1-3×109 cm-2. In contrast, a combination of Si doping and compressive growth stress has a synergistic effect on dislocation reduction. A simple 210 nm transition layer based on this understanding, the lowest reported yet, yields GaN layers that are crack free and have lower <1x109 cm-2 dislocation density, than those obtained by the aforementioned more complicated schemes. High electron mobility transistor characteristics performance on the probe GaN layers obtained on these transition layers supports the structural observations above.

Gallium nitride (GaN) high-electron-mobility transistors (HEMTs) are favored for their smaller specific on-resistance, lower switching losses, and higher theoretical temperature limits as compared to traditional silicon (Si) power switches. They have the potential to dramatically increase the power density and efficiency of power electronics systems by replacing traditional Si-based switches. However, GaN HEMTs have a faster switching speed compared to their Si-based counterparts. Minimizing the parasitic loop inductances of the GaN HEMT package is crucial for reducing electromagnetic interference (EMI) noise and voltage spikes. Another concern with GaN HEMTs comes from their lower thermal conductivity and smaller die size. The HEMTs generally have a higher heat flux density, and accordingly, demand better heat dissipation. Thus, innovations are needed for making GaN HEMT packages with low parasitic inductances and higher thermal performances to further their applications in high-frequency, high-power-density converters. To reduce loop inductance, other researchers have embedded GaN HEMTs in a printed circuit board (PCB) and used plated vias for interconnections and heat dissipation. However, this approach requires more complex manufacturing steps and has lower thermal performance. This dissertation introduces different embedded packaging techniques for 650V, 150A GaN HEMTs; this method involves interconnecting the bare chips between direct-bonded copper (DBC) and a PCB or between two DBCs, as discussed in Chapter 2. Vertical interconnections by gold pins and silver rods are introduced and implemented in embedded packages to limit the parasitic loop inductance within 1.5 nH and parasitic resistances within 1.5 mΩ. The thermal performance of the embedded GaN HEMT packages is experimentally verified in Chapter 2; then, the junction-to-case thermal resistance (RthJC) measurement is discussed in Chapter 3. The common temperature-sensitive electrical parameters (TSEPs) of a GaN HEMT for junction temperature measurement lack sufficient sensitivity or stability due to the electron-trapping effect. The non-uniform distribution of the case temperature and a large temperature gradient between the case and heatsink also make it difficult to accurately measure the case temperature. In Chapter 3, gate-to-gate resistance (Rg2g) is selected as the TSEP for junction temperature measurement. The stacked thermal interface material (TIM) technique was used to reduce errors in case temperature measurement. This technique was implemented in a custom GaN HEMT package and in embedded GaN HEMT packages for measuring junction-to-case thermal resistance. The discrepancy between measurement and simulation is less than 20%, and the junction-to-case thermal resistance for embedded packages is within 0.1 °C/W. Chapter 4 evaluates the reliability of the GaN HEMT embedded packages developed in Chapter 2 by utilizing a power cycling test. Monitoring the junction temperature of the embedded packages online is challenging during the power cycling test. Other approaches have used the on-resistance as the TSEP in order to monitor junction temperature for GaN HEMTs but this is not accurate due to electron trapping. As discussed in Chapter 3, Rg2g is chosen as the TSEP to monitor the junction temperature without worrying about the influence of electron trapping, and this approach cycles the embedded packages at 75 A from 25°C to 125°C. The packages can endure 23,000 power cycles before failure. This work is the first to develop, fabricate, and characterize embedded packages for 650V, 150A GaN HEMT bare chips. These embedded packages with high-power-rated GaN HEMT bare dice provide an opportunity to reduce the number of paralleled power switches, reduce the system's cooling size, and increase the system's power density. In addition, this work is the first to develop the junction-to-case thermal resistance measurement technique by gate-to-gate electrical resistance and stacked-TIM for GaN HEMT packages. The technique helps enable solid thermal design for power electronics systems. / Doctor of Philosophy / Power switches are everywhere in our daily life. They are the fundamental elements in power converters for converting power to electric vehicles. As global power demand for these applications continues to increase, high levels of both efficiency and power density are crucial for power switches. However, traditional silicon-based switches are already very mature, and their properties are very close to their theoretical limits. For further improvement, researchers have tried to replace traditional Si switches with wide-bandgap switches, which have much higher theoretical limits. Gallium nitride high-electron-mobility transistors (GaN HEMTs) are one of the candidates. However, packaging these switches (GaN HEMTs) is challenging due to their initial properties. They naturally switch very quickly and have smaller sizes compared to traditional Si-based switches. The fast switching speed brings high dv/dt and di/dt during the switching period. It causes voltage spikes and electromagnetic interference (EMI) issues. And the smaller size contributes to higher heat flux density, thus requiring more efficient heat dissipation. To solve the challenge of packaging GaN HEMTs, this dissertation has developed embedded packaging techniques to achieve quiet switching and good heat dissipation. These packaging techniques enable GaN HEMTs' advantages and increase the power density and efficiency of power electronics systems. To experimentally verify the thermal performance of the embedded packages developed a junction-to-case thermal resistance measurement technique was introduced. The thermal resistance of a custom GaN HEMT package was measured, as were those of the embedded packages CPES also developed. The simulation results and the experimental results are close to each other. Finally, to further evaluate whether or not the newly developed embedded packages are reliable, power cycling tests were carried out at I = 75 A. The packages survived over 23,000 cycles before failure.

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The effect of hot phonons and the influence of macroscopic polarization-induced built-in fields on the performance of III-V nitride devices are investigated. Self-heating due to hot phonons is analyzed in AlGaN/GaN high electron mobility transistors (HEMTs). Thermal transport by acoustic phonons in the diffusive limit is modeled using a two-dimensional lattice heat equation. The effect of macroscopic polarization charges on the operation of blue and green InGaN-based quantum well structures is presented. To characterize these structures, the electronic part of the two-dimensional quantum well laser simulator MINILASE is extended to include nitride bandstructure and material models. A six-band k.p theory for strained wurtzite materials is used to compute the valence subbands. Spontaneous and piezoelectric polarization charges at the interfaces are included in the calculations, and their effects on the device performance are described. Additionally, k.p Hamiltonian for crystal growth directions that minimize the polarization-induced built-in fields are modeled, and valence band dispersion for the non-polar and semi-polar planes are also calculated. Finally, a design parameter subspace is explored to suggest epitaxial layer structures which maximize gain spectral density at a target wavelength for green InxGa1-xN-based single quantum well active regions. The dependence of the fundamental optical transition energy on the thickness and composition of barriers and wells is discussed, and the sensitivity of gain spectral density to design parameters, including the choice of buffer layer material, is investigated.

L’intégration monolithique hétérogène de composants III-N sur silicium (Si) offre de nombreuses possibilités en termes d’applications. Cependant, gérer l’hétéroépitaxie de matériaux à paramètres de maille et coefficients de dilatation très différents, tout en évitant les contaminations, et concilier des températures optimales de procédé parfois très éloignées requière inévitablement certains compromis. Dans ce contexte, nous avons cherché à intégrer des transistors à haute mobilité électronique (HEMT) à base de nitrure de Gallium (GaN) sur substrat Si par épitaxie sous jets moléculaires (EJM) en vue de réaliser des circuits monolithiques GaN sur CMOS Si. / The monolithic integration of heterogeneous devices and materials such as III-N compounds with silicon (Si) CMOS technology paves the way for new circuits applications and capabilities for both technologies. However, the heteroepitaxy of such materials on Si can be challenging due to very different lattice parameters and thermal expansion coefficients. In addition, contamination issues and thermal budget constraints on CMOS technology may prevent the use of standard process parameters and require various manufacturing trade-offs. In this context, we have investigated the integration of GaN-based high electron mobility transistors (HEMTs) on Si substrates in view of the monolithic integration of GaN on CMOS circuits.