The purpose of this thesis is to examine multi-core technology. Multi-core architecture provides benefits such as less power consumption, scalability, and improved application performance enabled by thread-level parallelism.

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references.

Not available

The main contribution of this dissertation is the demonstration of the impact of a new emerging technology called 3D-integration technology on conventional high-performance microprocessors. 3D-integration technology stacks active devices in the vertical dimension in addition to the conventional horizontal dimension. The additional degree of connectivity in the vertical dimension enables circuit designers to replace long horizontal wires with short vertical interconnects, thus reducing delay, power consumption, and area. To adapt planar microarchitectures to 3D-integrated designs, we study several building blocks that together comprise a substantial portion of a processor s total transistor count. In particular, we focus our attention on three basic circuit classes: static random access memory (SRAM) circuits, associative/CAM logic circuits, and data processing in conventional high-performance processors. We propose 2-die-stacked and 4-die-stacked 3D-integrated circuits to deal with the constraints of the conventional planar technology. We propose high-performance 3D-integrated microprocessors and evaluate the impact on performance, power, and temperature. We demonstrate two different approaches to improve performance: clock speed (3D-integrated processors with identical microarchitectural configurations as the corresponding planar processor run at a higher clock frequency), and IPC (3D-integrated processors accommodate larger-sized modules than the planar processors for the same frequency). We demonstrate the simultaneous benefits of the 3D-integration and highlight the power density and thermal issues related to the 3D-integration technology. Next, we propose microarchitectural techniques based on significance partitioning and data-width locality to effectively address the challenges of power density and temperature. We demonstrate that our microarchitecture-level techniques can effectively control the power density issues in the 3D-integrated processors. The 3D-integrated processors provide a significant performance benefit over the planar processors while simultaneously reducing the total power. The simultaneous benefits in multiple objectives make 3D-integration a highly desirable technology for use in building future microprocessors. One of the key contributions of this dissertation is the temperature analysis that shows that the worst-case temperatures on the 3D-integrated processors can be effectively controlled using microarchitecture level techniques. The 3D-integration technology may extend the applicability of Moore s law for a few more technology generations.

Sustaining high performance demand has led to the development of manycore processors. These manycore processors have thermal properties which are different from conventional processors. In order to understand the thermal characteristics of such manycore processors, we have developed a modeling environment with a rich set of features which can be used to used to model different scenarios in manycore processors. Using this modeling framework, we have developed a thermal management policy called 'Weight based management policy'. We have also developed a GUI based modeling tool which can be integrated into the computer architecture curriculum so as to enable students to understand the importance of thermal limitations right during the design phase.

This thesis describes the efficient design of a future many-core processor that can provide higher performance under the limited chip power budget. To achieve such a goal, this thesis first develops an analytical framework within which computer architects can estimate achievable performance improvement of different many-core architectures given the same power budget. From this study, this thesis found that a future many-core processor needs (1) energy-efficient parallel cores and (2) a high-performance sequential core. Based on these observations, this thesis proposes an energy-efficient broad-purpose acceleration layer that can be snapped on top of a conventional general-purpose processor. In addition to such an energy-efficient parallel cores, this thesis also proposes different architectural techniques to further boost the performance of sequential computation while those parallel cores are idle. In particular, this thesis develops low-cost architectural techniques to enhance the memory performance of a host core by utilizing those idle parallel cores. This idea is evaluated in two different system architectures: one with the aforementioned acceleration layer and the other with an emerging integrated CPU and GPU chip.

For semiconductor processors temperature increases leakage current, which in turn in- creases the temperature of the processor. This increase in heat is seen by other parts of the processor since heat is diffusive across a processor die. In this way, cores are thermally coupled to one another such that when the temperature of one core increases, the temperatures of all cores on the same die can also increase. This increase in temperature and power consumption is not accompanied by any increase in performance. Cores on a chip can also be performance coupled to one another since cores can share data between them. These interactions between cores present new challenges to microarchitects who seek to optimize the energy consumption of a chip multiprocessor (CMP) comprised of multiple symmetric or asymmetric processing cores. This thesis seeks to understand and model the impact of thermal coupling effects between adjacent cores in a chip multiprocessor starting with measurements with a commercial multi-core processor. The hypothesis is that the thermal coupling of compute cores will be influenced by the adjacent core’s performance characteristics. Specifically, we expect thermal coupling is related to the nature of the workloads, e.g. compute intensive workloads will increase coupling over memory intensive workloads. However, we find that simpler parameters such as frequency of operation have more impact on coupling behaviors than the workload behaviors such as memory intensity or instruction retirement rates. A model is developed to capture thermal coupling effects and enable schemes to mitigate its impact.

This thesis introduces energy and performance optimization techniques for high-performance processors. Our optimization techniques target both single processors and chip multiprocessors (CMPs). In single processors, we exploit trivial instructions to improve energy and performance. Trivial instructions are those instructions whose output can be determined without performing the actual computations. We show that bypassing such unnecessary computations reduces energy while improve performance. Performance improvement achieved by skipping executing trivial instructions depends on how early such instructions are identified. We use value prediction to detect trivial instructions with high accuracy and as soon as possible. Consequently, we improve performance over a processor that bypasses trivial instructions without using speculation. In CMPs, we introduce two techniques to improve energy of interconnect and caches Conventional snoopy based chip multiprocessors take an aggressive approach broadcasting snoop requests to all nodes. In addition, each node checks all received requests. This approach reduces the latency of cache to cache transfer misses at the expense of increasing energy. We exploit this design inefficiency and introduce two optimization techniques in CMPs. First, and at the requester end, we introduce speculative selective request (SSR) to reduce energy consumption in the binary tree interconnect. In SSR, we send the request only to the node more likely to have the missing data. We reduce energy as we limit accesses only to the interconnect components between the requestor and the supplier node. Second, and at the receiving end, we propose speculative tag lookup (STL) to reduce energy consumption in data caches. We filter those accesses more likely to miss in the L1, cache. Using shared memory applications, we show that SSR and STL improve energy of interconnect and caches significantly with negligible performance loss and hardware overhead.

Thesis (M.Eng.). / Written for the Dept. of Electrical and Computer Engineering. Title from title page of PDF (viewed 2009/06/17). Includes bibliographical references.

Thesis (Ph. D.)-- State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Computer Science, 2009.