Since the emergence of solid state devices onto the storage scene, improvements in capacity and price have brought them to the point where they are becoming a viable alternative to traditional magnetic storage for some applications. Current file system and device level I/O scheduler design is optimized for rotational magnetic hard disk drives. Since solid state devices have drastically different properties and structure, we may need to rethink the design of some aspects of the file system and scheduler levels of the I/O subsystem. In this thesis, we consider the current approach to I/O scheduling and show that the current scheduler design may not be ideally suited to solid state devices. We also present a framework for extracting some device parameters of solid state drives. Using the information from the parameter extraction, we present a new I/O scheduler design which utilizes the structure of solid state devices to efficiently schedule writes. The new scheduler, implemented on a 2.6 Linux kernel, shows up to 25% improvement for common workloads.

This thesis includes two topics. The first topic is a data dispatcher design of a digital image processor for plasma display panels, which can be used in a 42-inch plasma display panel (PDP). The second one is a low-power small-area digital I/O cell design. The data dispatcher is applied to a 42-inch panel, which is produced by AUO corporation, as a test platform. It comprises FPGAs and RAMs to carry out data dispatching. The solution is verified to provide a better image quality, while the cost is also reduced. Regarding the low-power small-area digital I/O cell, we propose a totally different concept in contrast to traditional I/O cells. It is focused on low power consumption and small area. The proposed design is carried out by TSMC 1P5M 0.25 mm CMOS process at 2.5 V power supply. The power consumption is measured to be at least 51.4% less than prior works. The area is proven to be at least 44% more efficient.

<p>This study investigated the possibility of implementing three standards, Transistion Minimized Differential Signaling (TMDS) and two versions of Stub Series Terminated Logic (SSTL), for inter-chip communication in a specific manufacturing process. The two SSTL standards were implemented in one transceiver system while TMDS was implemented in a separate system. The evaluation was done with Spice simulations on schematic level with some parasitic capacitance and resistance. The idea was to investigate the possibility of implementing these standards and get an idea of eventual shortcomings. In order to create models as a basis for evaluation, simulation environments with models for circuit board and packages were created and transmitters and receivers were designed. During verification, variations in the process and different conditions as temperatureand voltages were considered. Some simplifications were made. All resistors have been assumed ideal and so have bias currents and bias voltages. Further more, parasitics from wires and other objects were missing due to the fact that the netlists came from electrical design and were not extracted from layout. The results showed that it is possible to implement SSTL in the desired semiconductor process. And so is the TMDS receiver. However some questions about the TMDS transmitter remain. Firstly, I see no theoretical possibility to get as short rise and fall time, with the specified load, as stated in the standard. Secondly, the opening in the eye diagram is large and has a good margin but when designing a TMDS transmitter one has to be careful in order to avoid overshoot. Apart from that, package and circuitboard has to be chosen so that they do not limit the system.</p>

This thesis focuses on the engineering of algorithms for massive data sets. In recent years, massive data sets have become ubiquitous and existing computing applications, for the most part, cannot handle these data sets efficiently: either they crash or their performance degrades to a point where they take unacceptably long to process the input. Parallel computing and I/O-efficient algorithms provide the means to process massive amounts of data efficiently. The work presented in this thesis makes use of these techniques and focuses on obtaining practically efficient solutions for specific problems in computational geometry and graph theory. We focus our attention first on skyline computations. This problem arises in decision-making applications and has been well studied in computational geometry and also by the database community in recent years. Most of the previous work on this problem has focused on sequential computations using a single processor, and the algorithms produced are not able to efficiently process data sets beyond the capacity of main memory. Such massive data sets are becoming more common; thus, parallelizing the skyline computation and eliminating the I/O bottleneck in large-scale computations is increasingly important in order to retrieve the results in a reasonable amount of time. Furthermore, we address two fundamental problems of graph analysis that appear in many application areas and which have eluded efforts to develop theoretically I/O-efficient solutions: computing the strongly connected components of a directed graph and topological sorting of a directed acyclic graph. To approach these problems, we designed algorithms, developed efficient implementations and, using extensive experiments, verified that they perform well in practice. Our solutions are based on well understood algorithmic techniques. The experiments show that, even though some of these techniques do not lead to provably efficient algorithms, they do lead to practically efficient heuristic solutions. In particular, our parallel algorithm for skyline computation is based on divide-and-conquer, while the strong connectivity and topological sorting algorithms use techniques such as graph contraction, the Euler technique, list ranking, and time-forward processing.

Evolutionary psychological principles were applied to the issue of sexual harassment to investigate whether the gender, power, and mate value of harassers were related to perceptions of sexual harassment. One hundred and sixty heterosexual men and women were given descriptions of a target individual whose mate value and power was manipulated, and three behavioural vignettes involving imagined interactions with the target individual. Participants rated their perceived level of sexual harassment (the dependent variable) stemming from the imagined interactions. Participants also provided ratings of their self perceived level of attractiveness, attitude towards social-sexual communication in the workplace, and experience with social-sexual communication in the workplace. As predicted, females perceived higher levels of sexual harassment than males, and participants perceived higher levels of sexual harassment from low mate-value target individuals than high mate-value target individuals. Against predictions, no result was found for power. Additionally, self perceived level of attractiveness was found to moderate the relationship between gender and perceived sexual harassment, and attitude towards social-sexual communication in the workplace was found to moderate the relationship between mate value and perceived sexual harassment. Implications and explanations are discussed with reference to workplace issues, and evolutionary psychology.

Evolutionary psychological principles were applied to the issue of sexual harassment to investigate whether the gender, power, and mate value of harassers were related to perceptions of sexual harassment. One hundred and sixty heterosexual men and women were given descriptions of a target individual whose mate value and power was manipulated, and three behavioural vignettes involving imagined interactions with the target individual. Participants rated their perceived level of sexual harassment (the dependent variable) stemming from the imagined interactions. Participants also provided ratings of their self perceived level of attractiveness, attitude towards social-sexual communication in the workplace, and experience with social-sexual communication in the workplace. As predicted, females perceived higher levels of sexual harassment than males, and participants perceived higher levels of sexual harassment from low mate-value target individuals than high mate-value target individuals. Against predictions, no result was found for power. Additionally, self perceived level of attractiveness was found to moderate the relationship between gender and perceived sexual harassment, and attitude towards social-sexual communication in the workplace was found to moderate the relationship between mate value and perceived sexual harassment. Implications and explanations are discussed with reference to workplace issues, and evolutionary psychology.

Out-of-Core simulation systems often produce a massive amount of data that cannot t on the aggregate fast memory of the compute nodes, and they also require to read back these data for computation. As a result, I/O data movement can be a bottleneck in large-scale simulations. Advances in memory architecture have made it feasible and a ordable to integrate hierarchical storage media on large-scale systems, starting from the traditional Parallel File Systems (PFSs) to intermediate fast disk technologies (e.g., node-local and remote-shared NVMe and SSD-based Burst Bu ers) and up to CPU main memory and GPU High Bandwidth Memory (HBM). However, while adding additional and faster storage media increases I/O bandwidth, it pressures the CPU, as it becomes responsible for managing and moving data between these layers of storage. Simulation systems are thus vulnerable to being blocked by I/O operations. The Multilayer Bu er System (MLBS) proposed in this research demonstrates a general and versatile method for overlapping I/O with computation that helps to ameliorate the strain on the processors through asynchronous access. The main idea consists in decoupling I/O operations from computational phases using dedicated hardware resources to perform expensive context switches. MLBS monitors I/O tra c in each storage layer allowing fair utilization of shared resources. By continually prefetching up and down across all hardware layers of the memory and storage subsystems, MLBS transforms the original I/O-bound behavior of evaluated applications and shifts it closer to a memory-bound or compute-bound regime. The evaluation on the Cray XC40 Shaheen-2 supercomputer for a representative I/Obound application, seismic inversion, shows that MLBS outperforms state-of-the-art PFSs, i.e., Lustre, Data Elevator and DataWarp by 6.06X, 2.23X, and 1.90X, respectively. On the IBM-built Summit supercomputer, using 2048 compute nodes equipped with a total of 12288 GPUs, MLBS achieves up to 1.4X performance speedup compared to the reference PFS-based implementation. MLBS is also demonstrated on applications from cosmology, combustion, and a classic out-of-core computational physics and linear algebra routines.

With the advent of emerging "e-Science" applications, today's scientific research increasingly relies on petascale-and-beyond computing over large data sets of the same magnitude. While the computational power of supercomputers has recently entered the era of petascale, the performance of their storage system is far lagged behind by many orders of magnitude. This places an imperative demand on revolutionizing their underlying I/O systems, on which the management of both metadata and data is deemed to have significant performance implications. Prefetching/caching and data locality awareness optimizations, as conventional and effective management techniques for metadata and data I/O performance enhancement, still play their crucial roles in current parallel and distributed file systems. In this study, we examine the limitations of existing prefetching/caching techniques and explore the untapped potentials of data locality optimization techniques in the new era of petascale computing. For metadata I/O access, we propose a novel weighted-graph-based prefetching technique, built on both direct and indirect successor relationship, to reap performance benefit from prefetching specifically for clustered metadata serversan arrangement envisioned necessary for petabyte scale distributed storage systems. For data I/O access, we design and implement Segment-structured On-disk data Grouping and Prefetching (SOGP), a combined prefetching and data placement technique to boost the local data read performance for parallel file systems, especially for those applications with partially overlapped access patterns. One high-performance local I/O software package in SOGP work for Parallel Virtual File System in the number of about 2000 C lines was released to Argonne National Laboratory in 2007 for potential integration into the production mode.

MPI-IO, the parallel I/O functionality of MPI-2, is a portable interface designed specifically to achieve high-performance. This thesis proposes fundamental design criteria influencing the performance of a portable high performance I/O middleware. This thesis hypothesizes that overlap of I/O and computation and agglomeration of I/O requests based on an application's access pattern improve the performance of a portable parallel I/O implementation. The work included the development of MercutIO, a complete, portable, high performance MPI-IO implementation. MercutIO achieves portability through the Bulldog Abstract File System, a portable, efficient non-collective I/O interface, also developed in this thesis work. A new data access model based on non-blocking semantics is presented here. Two new I/O metrics (degree of overlapping and degree of non-contiguity) as well as parallel I/O benchmarks essential in the performance appraisal of a parallel I/O implementation are introduced in this thesis.

Traditional file access interfaces rely on ubiquitous transports that impose severe restrictions on performance and prove insufficient for adaptation to parallel Input/Output (I/O). Remote Direct Memory Access based (RDMA-based) approaches are aimed at moving data between different process address spaces with streamlined mediation and reduced involvement of the operating system using synchronization semantics that are different from ubiquitous transports. This thesis studies the adaptability of RDMA-based transports to parallel I/O. Combining RDMA semantics with parallel I/O leads to overhead reduction by overlapping communication and computation and by bandwidth enhancement. Although parallel I/O tends to increase latency in certain cases, use of RDMA techniques mitigate on this effect.