The thesis deals with the design of digital I/O card with USB connectivity for Honeywell spol. s r.o. – HTS CZ o.z. company. The main objective is the delay elimination between reading the current state of the inputs and outputs setting which occurs on the actual used commercial card. Further initial analysis outlines possible solutions at the beginning of the work. One of chapters describes USB communication interface, including its com- munications protocol and USB driver implementation on the operating system Microsoft Windows. The digital card has four I/O ports consisting of eight lines. All ports have built-in protection against overcurrent and ESD protection. Digital isolator is used for USB. Power is supplied via USB, but it is optionally possible to connect an external power source. The last part of the thesis is focused on the card driver design.

Med höga belastningar inom dagens process- och tillverkningsindustri är det mycket vanligt med automatiserade processer, för att skapa dessa processer används oftast PLC eller SCADA system. System som dessa är ofta dyra varför det kan vara svårt för mindre företag att investera i och hålla systemen löpande uppdaterade. Därför skall det i detta projekt visas att det finns möjlighet att utveckla automatiserade processer till rimliga kostnader. Med hög efterfrågan av automationssystem är det också viktigt att i utbildningsyfte lära ut om denna teknik. För det krävs det enkla system för studenter att kunna konstruera och programmera mindre processer. Detta skall visas genom att i utvecklingsmiljön Codesys konstruera ett sorteringssystem med SoftPLC funktionsblock där programvaran i sin tur skall exekveras i en Raspberry Pi hårdvara. Genom SoftPLC gör man systemet kompatibelt för anslutning av ett stort antal I/O-enheter av olika slag. Detta ger en flexibilitet för företag att till rimlig kostnad löpande vidareutveckla befintliga system. Den utvecklade programvarans huvudsakliga uppgift är att skapa logiska samband och styrningar kopplade till den information som inhämtas från de till CPU-enheten anslutna programerabara distribuerade I/O-enheter. Programvarans funktionalitet konstruerades för att få ett objekt att längs ett löpande band färdas runt och sorteras beroende på dess material och färg utan extern hjälp. Den färdiga konstruktionen gjorde det möjligt för en kloss att ta sig runt utan extern hjälp. Med detta program var det möjligt för processen att kunna sortera svart, vit och metalliska klossar, för att sen placera ut klossarna på specifika löpband. Som slutsats konstateras att det är fullt rimligt att skapa modulära automatiserade processer med god precision till ett rimligt pris. Detta genom användande av open-source programvara som exekverar i på marknaden prisvärda CPU-enheter / With a higher workload in today’s process and manufacturing industry has it become more popular with automated systems and processes, were SCADA and PLC is the leading development system. Systems like this are often expensive and can because of that be hard to maintain for smaller companies to keep updated. In this project it will be possible to develop an automated process for reasonable cost. With high demand of automation system, it is also important in educational purposes to teach and develop such systems. Therefor it is important with simple system to build and program.  By using the developing tool Codesys build a sorting system with SoftPLC function block where this software will be executed on a Raspberry Pi.  With SoftPLC it will be possible to make it compatible for connection with vast majority of I/O-units. This makes it flexible for companies to continue developing their firmware for a lower cost. The developed software main task is to create logical connections and controls that is gathered from the CPU connections programmable I/O-units. The software was created for an object to be able to travel on conveyor belt and be sorted depending on its colour without any external help. The complete setup made it possible for an object to travel without any external help. With the software it was possible for the process to sort black, white and metallic colour on the object, to then be able to place these on specific conveyor belt depending on its colour. As a conclusion to this project, it is possible to make automated processes for a reasonable price with good precision. This by using open-source software which can be downloaded on low-cost CPU-units.

De nombreuses applications scientifiques utilisent et génèrent d'énormes quantités de données. Ces applications qui exploitent des modèles d'accès parallèles spécifiques (principalement des accès disjoints) sont souvent pénalisées par des systèmes de stockage inadaptés. Pour éviter les dégradations de performances, les bibliothèques d'Entrées/Sorties parallèles telles que ROMIO sont généralement utilisées pour agréger les petites requêtes séparées en de plus grosses contiguës habituellement plus performantes. Toutefois, les optimisations apportées pour un programme ne tiennent pas compte de l'ensemble des interactions avec d'autres applications s'exécutant en concurrence sur la grappe. La conséquence est que ces routines spécifiques visant à optimiser les accès d'une application vont s'avérer inutiles, car leur effet va être perturbé par les autres applications !<br /><br />Ce document décrit une nouvelle approche, appelée aIOLi, permettant le<br />contrôle, le réordonnancement et la régulation de l'ensemble des interactions générées par les différentes applications s'exécutant simultanément sur une grappe et ce, en s'appuyant uniquement sur l'interface POSIX.<br /><br />Dans un tel contexte, la performance, l'interactivité et l'équité sont des critères pour lesquels il est important de trouver un bon compromis. Pour y parvenir, une stratégie d'ordonnancement globale prenant en compte également les problématiques d'Entrées/Sorties parallèles locales aux applications a été définie. Le service aIOLi consiste en un support d'ordonnancement générique pouvant être rattaché à différentes parties d'un système de fichiers. L'exécution concurrente de jeux de tests IOR sur un serveur NFS traditionnel ont montré des améliorations particulièrement significatives pour les accès en lecture en comparaison aux performances pouvant être atteintes avec les routines POSIX ou MPI I/O.

High-speed serial input-output (I/O) link has required advanced equalization and modulation techniques to mitigate inter-symbol interference (ISI) caused by multi-Gb/s signaling over band-limited channels. Increasing demands for transceiver power and area complexity has leveraged on-going interest in analog-to-digital converter (ADC) based link, which allows for robust equalization and flexible adaptation to advanced signaling. With diverse options in ISI control techniques, link performance analysis for complicated transceiver architectures is very important. This work presents advanced statistical modeling for ADC-based link, performance comparison of existing modulation and equalization techniques, and proposed hybrid ADC-based receiver that achieves further power saving in digital equalization. Statistical analysis precisely estimates high-speed link margins at given implementation constrains and low target bit-error-rate (BER), typically ranges from 1e-12 to 1e-15, by applying proper statistical bound of noise and distortion. The proposed statistical ADC-based link modeling utilizes bounded probability density function (PDF) of limited quantization distortion (4-6 bits) through digital feed-forward and decision feedback equalizers (FFE-DFE) to improve low target BER estimation. Based on statistical modeling, this work surveys the impact of insufficient equalization, jitter and crosstalk on modulation selection among two and four level pulse amplitude modulation (PAM-2 and PAM-4, respectively) and duobinary, and ADC resolution reduction performance by partial analog equalizer (PAE). While the information of channel loss at effective Nyquist frequency and signaling constellation loss initially guides modulation selection, the statistical analysis results show that PAM-4 best tolerates jitter and crosstalk, and duobinary requires the least equalization complexity. Meanwhile, despite robust digital equalization, high-speed ADC complexity and power consumption is still a critical bottleneck, so that PAE is necessitated to reduce ADC resolution requirement. Statistical analysis presents up to 8-bit resolution is required in 12.5Gb/s data communications at 46dB of channel loss without PAE, while 5-bit ADC is enough with 3-tap FFE PAE. For optimal ADC resolution reduction by PAE, digital equalizer complexity also increases to provide enough margin tolerating significant quantization distortion. The proposed hybrid receiver defines unreliable signal thresholds by statistical analysis and selectively takes additional digital equalization to save potentially increasing dynamic power consumption in digital. Simulation results report that the hybrid receiver saves at least 64% of digital equalization power with 3-tap FFE PAE in 12.5Gb/s data rate and up to 46dB loss channels. Finally, this work shows the use of embedded-DFE ADC in the hybrid receiver is limited by error propagation.

Machine virtualization has become a cornerstone of modern datacenters. It enables server consolidation as a means to reduce costs and increase efficiencies. The communication endpoints within the datacenter are now virtual machines (VMs), not physical servers. Consequently, the datacenter network now extends into the server and last hop switching occurs inside the server. Today, thanks to increasing core counts on processors, server VM densities are on the rise. This trend is placing enormous pressure on the network I/O subsystem and the last hop virtual switch to support efficient communication, both internal and external to the server. But the current state-of-the-art solutions fall short of these requirements. This thesis presents new architectures and mechanisms for the network subsystem in virtualized servers to build efficient virtualization platforms. Specifically, there are three primary contributions in this thesis. First, it presents a new mechanism to reduce memory sharing overheads in driver domain-based I/O architectures. The key idea is to enable a guest operating system to reuse its I/O buffers that are shared with a driver domain. Second, it describes Hyper-Switch, a highly streamlined, efficient, and scalable software-based virtual switching architecture, specifically for hypervisors that support driver domains. The Hyper-Switch combines the best of the existing architectures by hosting the device drivers in a driver domain to isolate any faults and placing the virtual switch in the hypervisor to perform efficient packet switching. Further, the Hyper-Switch implements several optimizations, such as virtual machine state-aware batching, preemptive copying, and dynamic offloading of packet processing to idle CPU cores, to enable efficient packet processing, better utilization of the available CPU resources, and higher concurrency. This architecture eliminates the memory sharing overheads associated with driver domains. Third, this thesis proposes an alternate virtual switching architecture, called sNICh, which explores the idea of server/switch integration. The sNICh is a combined network interface card (NIC) and datacenter switching accelerator. This takes the Hyper-Switch architecture one step further. It offloads the data plane of the switch to the network device, eliminating driver domains entirely.

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This report is about a thesis that is performed in and for SYSteam Engineering AB in Motala. The thesis work is divided into three parts, study of the market, programming and electronics. The study part consists of examining and comparing different data acquisition systems for testing of different circuit boards, taking into account the modularity, real-time applications, mobility, environmental, interface hardware and software, to be able to define a general module-based data acquisition system in both hardware and software that enables for future developments. The programming part consists of getting started with Visual Studio, which integrates the Measurement Studio for C#. NET. Measurement Studio includes classes and user controls for testing and measuring and offers tools for acquisition, analysis and presentation of real world data. The programming has been the biggest part of the project, the orienting of test specification and to learn how to program and control the hardware according to the test conditions took the most of time. Electronics is the part that took the least time, which consists of orienting the test specification, connecting cables to the I/O modules and supplements the system with any components which is necessary to execute the various test cases. The result was a system consisting of a chassis with a number of modules that National Instruments offers and a test program consisting of three class levels that can be reused in different projects and for different test items.

In modern integrated circuits, electrostatic discharge (ESD) is a major problem that influences the reliability of operation, yield and cost of fabrication. ESD discharge events can generate static voltages beyond a few kilo volts. If these voltages are dissipated in the chip, high electric field and high current are generated and will destroy the gate oxide material or melt the metal interconnects. In order to protect the chip from these unexpected ESD events, special protection devices are designed and connect to each pin of the IC for this purpose. With the scaling of nano-metric processing technologies, the ESD design window has become more critical. That leaves little room for designers to maneuver. A good ESD protection device must have superior current sinking ability and also does not affect the normal operation of the IC. The two main categories of ESD devices are snapback and non-snapback ones. Non-snapback designs usually consist of forward biased diode strings with properties, such as low heat and power, high current carrying ability. Snapback devices use MOSFET and silicon controlled rectifier (SCR). They exploit avalanche breakdown to conduct current. In order to investigate the properties of various devices, they need to be modeled in device simulators. That process begins with realizing a technology specific NMOS and PMOS in the device simulators. The MOSFET process parameters are exported to build ESD structures. Then, by inserting ESD devices into different simulation test-benches, such as human-body model or charged-device model, their performance is evaluated through a series of figures of merit, which include peak current, voltage overshoot, capacitance, latch-up immunity and current dissipation time. A successful design can sink a large amount of current within an extremely short duration, while it should demonstrate a low voltage overshoot and capacitance. In this research work, an inter-weaving diode and SCR hybrid device demonstrated its effectiveness against tight ESD test standards is shown.

This thesis is composed of two parts : a 3¡ÑVDD bidirectional mixed-voltage-tolerant I/O buffer, and a 2¡ÑVDD output buffer with process and temperature compensation. In the first topic, a 3¡ÑVDD bidirectional mixed-voltage-tolerant I/O buffer, which is able to tolerate 3¡ÑVDD using stacking transistors in the output stage, is proposed. These transistors are biased by corresponding voltage levels which are generated by a dynamic gate bias generator and a floating N-well circuit when transmitting or receiving signals. In order to prevent the input stage transistors from gate-oxide overstress, an NMOS clamping technique is used to block high input voltages. This design can receive and transmit 0.9 V to 5.0 V (0.9/1.2/1.8/2.5/3.3/5.0 V) signals, which has been implemented using TSMC 1P6M 0.18 £gm CMOS process. The second topic shows a 2¡ÑVDD output buffer with process and temperature compensation using 1P6M 0.18 £gm CMOS process. In this design, a novel process and temperature variation detector is proposed to detect the corners of NMOS and PMOS, respectively. The driving capability of the output stage is enhanced at those corners with low output currents. By contrast, the driving currents is reduced at those corners with high output currents to reduce the variation of output slew rate.

The thesis is composed of tow topics: a fully bidirectional mixed- voltage-tolerant I/O cell using a new output stage circuit and a sub-3¡ÑVDD wide range fully bidirectional mixed-voltage-tolerant I/O cell. The first topic discloses a mixed-voltage-tolerant I/O cell implemented using 2P4M 0.35 £gm CMOS process, which uses a low static power dynamic gate bias generator providing three different logic voltage levels to the output stage to avoid gate oxide reliability and leakage current. The design also reveals a new output stage circuit, which enhances the output current to resolve the poor driving capability caused by the slow mobility and body effect of the stacked PMOS. The second topic shows a sub-3¡ÑVDD wide range fully bidirectional mixed-voltage-tolerant I/O cell using 1P6M 0.18 £gm CMOS process, which employs a new dynamic gate bias generator and a PAD voltage detector to provide appropriate gate biases. The design includes a new gate tracking circuit and a floating N-well circuit to avoid gate oxide reliability and leakage current, which relaxes the body effect at the output PMOS.